Arithmetic circuits play an important role in high-performance digital systems. The paper considers a generic architecture of hybrid prefix/carry-select arithmetic systems. A novel proof methodology is proposed to model and verify hybrid addition systems. Algebraic structures and first-order recursive equations are harnessed in proof derivations. Case studies on several typical classes of hybrid prefix/carry-select adders and special cases with pseudo-carries such as Ling's carry demonstrate the effectiveness of the proposed approach.

Adder circuits have been extensively studied. Their formal properties are well known, but the proofs are either incomplete or difficult to find. This short contribution intends to integrate all formal proofs related to adders in a single place and to add the details when necessary. The presentation is accessible to general VLSI designer. Another goal of this study is to put together relevant materials for the preparation of further formal studies in computer arithmetic. The presentation is made as concise as possible.

End-around-carry (EAC) adder is extensively used in microprocessor's floating-point units. This paper presents an algebraic characterization of an EAC adder's algorithm. A novel symbolic analysis approach is presented to prove the EAC adder's correctness. Algebraic structures and first-order recursive equations are harnessed in proof derivations. A hybrid prefix/EAC architecture is considered.

Several regular parallel trees have been proposed over the years to optimize logic depth, area, fan-out and interconnect count for logic circuits. In this paper, we propose a comparative study of different parallel prefix trees used in the design of a new end-around carry (EAC) adder targeting FPGA technology. This new adder is based on the fast 128-bit binary floating-point EAC adder which has been implemented in the IBM POWER6 microprocessor's fused multiply-add unit. The parallel prefix tree implemented on the IBM's EAC adder is a Kogge-Stone tree which has been chosen for its high performance and its low power consumption. Our comparative study highlights the main performance differences among fourteen different architecture configurations when targeting an FPGA EAC adder design. We focus on the area requirements and the critical path delay of these designs. Our experimental results show that there is one architecture configuration with the lower area requirement and the higher performance.

article Share on A note on “a mapping algorithm for computer-assisted exploration in the design of embedded systems” Authors: Gang Chen Portland State University, Portland, OR Portland State University, Portland, ORView Profile , Xiaoyu Song Portland State University, Portland, OR Portland State University, Portland, ORView Profile , Feng Liu National Lab of Parallel Distributed Processing, Hunan, China National Lab of Parallel Distributed Processing, Hunan, ChinaView Profile , Qingping Tan National Lab of Parallel Distributed Processing, Hunan, China National Lab of Parallel Distributed Processing, Hunan, ChinaView Profile , Fei He Tsinghua University, Beijing, P.R. China Tsinghua University, Beijing, P.R. ChinaView Profile Authors Info & Claims ACM Transactions on Design Automation of Electronic SystemsVolume 12Issue 401 September 2007pp 52–eshttps://doi.org/10.1145/1278349.1278365Published:01 September 2007Publication History 0citation220DownloadsMetricsTotal Citations0Total Downloads220Last 12 Months3Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access