Neural Architecture Search (NAS) aims to automate the design of neural networks, enabling the discovery of highly effective architectures. Recent advancements in NAS have shown significant success in identifying high-performing Transformer architectures for computer vision and natural language processing tasks. However, most NAS research has focused on supervised learning frameworks, which rely heavily on labeled data. This dependence on labeled data makes deploying these methods in real-world applications challenging due to the high cost of data annotation. Additionally, previous studies often prioritize model performance while neglecting generalization ability, particularly in scenarios with limited labeled data. To address these challenges, this study introduces a generalization-aware zero-shot proxy based on self-supervised learning. By combining this proxy with a complementary zero-shot proxy, we identify architectures that balance generalization ability and expressivity. Experimental results demonstrate that the architectures discovered using the proposed approach achieve competitive performance on the ImageNet and Wikitext-2 datasets while significantly reducing the required labeled data by up to 75% and 99%, respectively.

This paper presents the design and hardware implementation of an energy-efficient data detector for uplink cell-free (CF) MIMO networks. The design is based on the DMPACT CF MIMO detection algorithm proposed in [7], which beats other CF detection methods in terms of detection performance and computational complexity. We have proposed several novel techniques in this detector, including eigenvalue decomposition, CORDIC algorithms, and fast inverse square root calculations, to compute the Mahalanobis distances, reducing multiplication complexity by 81%. Additionally, Gaussian approximation was further proposed for complexity optimization. The final hardware design incorporates circuit sharing, outcome reuse, and pipelining to enhance circuit performance. Finally, synthesized using the 28nm CMOS technology, the proposed multi-core hardware operates at 667 MHz and achieves a 10.67 nJ/bit energy efficiency, beating the single-core approach by at least 16%.

Cell-free (CF) multiple input multiple output (MIMO) is gaining traction for B5G/6G wireless communication systems due to its heightened connectivity, spectral efficiency, and quality of service (QoS). Developing an efficient data detector is imperative to harness these attributes effectively in uplink transmissions. In this paper, we propose the DMPACT2 detector, a message-passing algorithm (MPA) variant that dynamically adjusts the factor graph (FG) based on achievable rate, allocating computing resources judiciously. Additionally, two low-complexity techniques are employed to save 99% of DMPACT2’s complexity, namely local minimum mean-squared error (MMSE)-based initial constellation truncation and log-likelihood ratio (LLR)-based constellation truncation. Simulation results demonstrate that the proposed adaptive FG boosts DMPACT2’s bit error rate (BER) to approach the BER lower bound of the optimal maximum likelihood (ML) detector under high Signal-to-Noise Ratio (SNR), indicating that DMPACT2 is very competitive with the optimal detection. Moreover, DMPACT2 attains a$10^{-2}$BER with a 3dB lower SNR than the best competitor using the same computational complexity. Furthermore, we propose a novel metric, power-normalized bit rate, which simultaneously accounts for throughput, BER, complexity, transmission power, and backhaul traffic in the cell-free context. In terms of the power-normalized bit rate, DMPACT2 exhibits superior performance compared to all other detectors.

With the rapid development of AI technology, neural network models have achieved amazinig success in the field of computer vision. In the context of image classification, Vision Transformer (ViT) models, by integrating self-attention and the Transformer architecture, stand out as a representation of stunning progress. Automated search for ViT-based models is imperative in the quest for optimal vision performance. Nevertheless, most existing Neural Architecture Search (NAS) algorithms either lack support for ViTs or demand very long search time. The TPC score and TPC-NAS [1] empower users to quickly, within minutes, explore hundreds of thousands of architectures based on a distinct ViT. In this paper, we enhance TPC-NAS and apply it to the ViT. First, the strong rank correlation (0.97) between the TPC score and accuracy confirms the effectiveness of the TPC score on ViT. Following that, TPC-NAS is customized to align with the characteristics of the ViT, introducing enhancements in the search space and methodology to facilitate finding optimal architectures. In the ImageNet image classification task, the TPC-NAS-discovered ViT model attains a Top-1 accuracy of 82.8% at 4G FLOPs, outperforming all other NAS methods. Finally, for several well-known ViT families, the ViT models discovered by TPC-NAS possess better performance than the corresponding baselines.

Hybrid beamforming has attracted considerable interest in the development of next-generation wireless communications operating in the terahertz (THz) band. The short wavelength of THz wave has enabled thousands of antennas to be tightly packed inside a small area to provide sharp and accurate beamforming. Unfortunately, the beam squint effect, which changes the direction of beams as the frequency shifts, can only be circumvented by introducing true-time-delay (TTD) lines in the hybrid beamformers. However, most previous works neglected the resolution limitation of the precoding hardware and assumed phase shifters (PSs) and TTDs with infinite resolution. This paper proposes two quantized hybrid beamforming algorithms for the PS-only hybrid architecture and the TTD-assisted hybrid beamformer. We use a gradient descent approach with differentiable soft quantization techniques to overcome quantizer discontinuity. The RF precoder and the baseband precoder are alternately updated to maximize the similarity with the optimal precoder. Simulation results demonstrate the effectiveness of the proposed algorithms. The proposed 3-bit PS-only beamformer can achieve near-optimal performance and outperform other low-resolution precoding methods in a moderate squint scenario. The proposed low-resolution TTD-assisted architecture can effectively compensate severe squint effect and achieves near-optimal performance.

In the training process of convolutional neural networks (CNN), a batch normalization (BN) layer is often inserted after a convolution layer to accelerate the convergence of CNN training. In this work, we propose a BN processor that supports both the training and inference processes. To speed up the training of CNN, the proposed work develops an efficient dataflow integrating a novel BN processor design and the processing elements for convolution acceleration. We exploited the similarities in the calculations required for the BN forward and backward passes by sharing hardware elements between both passes, therefore reducing the area overhead. In addition to functional verification of the BN processor, we also completed Automatic Placement & Routing (APR) and conducted post-APR simulation on neural network training. Finally, the proposed solution not only significantly speeds up the CNN training process, but also achieves hardware saving.

The mapping of DNA subsequences to a known reference genome, referred to as “short-read mapping”, is essential for next-generation sequencing. Hundreds of millions of short reads need to be aligned to a tremendously long reference sequence, making short-read mapping very time consuming. In this article, a high-throughput hardware accelerator is proposed so as to accelerate this task. A Bloom filter-based candidate mapping location (CML) generator and a folded processing element (PE) array are proposed to address CML selection and the Smith-Waterman (SW) alignment algorithm, respectively. It is shown that the proposed CML generator reduces the required memory access by 40 percent by employing a down-sampling scheme when compared to the Ferragina-Manzini index (FM-index) solution. The proposed hierarchical Bloom filter (HBF) that includes optimized parameters achieves a 1.5×104times acceleration over the conventional Bloom filter. The proposed memory re-allocation scheme further reduces the memory access time for the HBF by a factor of 256. The proposed folded PE array delivers a 1.2-to-3.2 times higher giga cell updates per second (GCUPS). The processing time can be further reduced by 53-to-72 percent by employing a fully pipelined PE array that allows for a tailored shift amount for seeding. The accelerator is realized on a Stratix V GX FPGA with 16GB external SDRAM. Operated at 200MHz, the proposed FPGA accelerator delivers a 2.1-to-11 times higher throughput with the highest 99 percent accuracy and 98 percent sensitivity compared to the state-of-the-art FPGA-based solutions.

In this paper, we present a real-time software-defined radio (SDR) solution for an LTE downlink transceiver in ultra dense networks (UDN). This SDR platform integrates the processing power of CPU and GPU and commercial RF transmitting and receiving frontend instruments. Most of the UDN receiver baseband processing is carried out via OpenCL programming language running on a GPU. In the over-the-air (OTA) UDN demonstration, we emulate three 4G LTE basestations: one strong interference macro basestation (MBS) and another weaker interference from a neighboring pico basestation (PBS), plus the serving PBS. The receiver implements all LTE MIMO-OFDM baseband processing and the data detection is achieved by a novel interference-aware MIMO detection scheme. An associated GUI displaying real-time channel estimation outcomes and UDN receiver performance is also developed. Finally, the prototype successfully demonstrates real-time reception of 10-MHz two-stream LTE signal under two interference sources.

Inter-cell interference (ICI) may considerably degrade the detection performance of receivers in heterogeneous networks (HetNets). To increase the spectrum efficiency per area, the cell ranges of small cells may be expanded, making the ICI problem more severe. Furthermore, to pursue higher data rate, spatial multiplexing is often applied, incurring inter-antenna interference (IAI). This paper presents a turbo receiver with a dual-loop dual-list update (TRDDU) structure that efficiently detects data signal deteriorated by both ICI and IAI. The proposed lists maintained several likely data vectors and interference vectors, facilitating the receiver to more efficiently determine the most-likely solution. In addition, a dual-loop update algorithm was proposed to enhance the iteration efficiency. Moreover, two design techniques were proposed to reduce the detection complexity. Simulation results showed that the error rate performance of TRDDU is close to that of a receiver in the ICI-free scenario. The complexity needed by TRDDU is only 3.5% that of the receiver that considers all possible interference vectors. In addition, the TRDDU complexity is only approximately 1.56 times that of a successive-interference-cancellation-based receiver. Finally, an over-the-air experiment was conducted to validate the effectiveness of the proposed TRDDU, and the results demonstrated the feasibility of this receiver in the field.

We propose an efficient iterative multiple-input multiple-output (MIMO) detection algorithm based on the local search. Specifically, since the MIMO channel matrix twists the lattice structure of the received symbols, the proposed channel-aware local search (CA-LS) defines its search neighborhood according to the instantaneous channel realization. Such channel-dependent neighborhood can be efficiently identified by using the sphere decoder in a set that comprises the differences between pairs of QAM vectors, which is termed as delta vectors. The delta vectors with small quadratic norms with respect to the channel matrix are identified and then used as the search directions of the CA-LS. Features like sparsity and non-uniformity of delta vectors are exploited to reduce the SD complexity. Furthermore, by reformulating the detection criterion, the log-likelihood ratio (LLR) computations and searches of the CA-LS are greatly simplified. Numerical simulations demonstrate that compared with other practical iterative MIMO detectors, e.g., the list sphere decoder, the CA-LS achieves superior performance in both error rate and complexity aspects.

This paper presents a real-time implementation of both a fountain code decoder and a MIMO-OFDM receiver for a wireless video streaming system. The development of the physical layer conforms to the specifications of the Wireless LAN standard, while the limited MAC functionality is based on custom specifications. In order to realize a real-time wireless video streaming system that has a low latency, fountain code, which does not require re-transmission, is adopted. However, since the conventional decoding algorithm for fountain code cannot maintain the high-throughput requirements of real-time streaming, hardware design is implemented based on the Sherman-Morrison algorithm for fountain code decoders, thereby overcoming the problem. The results verify that the proposed fountain code decoder is able to outperform the conventional decoder. Consequently, the validity of the proposed real-time video streaming system is demonstrated.

The inter-cell interference (ICI) may considerably degrade the system performance of heterogeneous networks (HetNets) and is generally tackled by the transmitters, which often leads to lower spectrum efficiency. To avoid such disadvantage, this work presents a new receiver function that identifies the precoders assigned to active users in interfering cells, and thus enables more effective ICI mitigation. We theoretically derive the design criterion and analyze the performance of the receiver equipped with the proposed active precoder identification (API) scheme. We also propose two low-complexity techniques: the recursive structure based on the Sherman-Morrison formula/matrix determinant lemma, and the mode-switching technique adapting the search space on-the-fly. Numerical simulations demonstrate that such receiver can achieve error rate performance close to a receiver with perfect knowledge of the active precoders. The recursive structure achieves 68% complexity saving, while the mode-switching technique further increases the saving to 83%.

The performance of heterogeneous networks (Het-Nets) is strongly affected by inter-cell interference. Instead of relying on coordination among base stations, this study presents a new receiver block that identifies the precoders assigned to active users in an adjacent cell. Equipped with this proposed active precoder identification (API), the inter-cell interference at the receiver becomes feasible. The low complexity API is based on the maximum likelihood (ML) criterion and Sherman-Morrison formula. Moreover, by leveraging the fact that the list of active precoders often changes one precoder at a time, an efficient mode-switching API algorithm is proposed for further complexity reduction. Demonstrated by numerical results, the proposed API enables the receiver to achieve error rate performance close to that of the receiver with perfect knowledge of the active precoders used for transmission in the adjacent cell.

This paper presents a turbo receiver using the proposed ICI-aware Dual-List (IDL) MIMO detection method that can efficiently detect signals deteriorated by both inter-carrier interference (ICI) and inter-antenna interference (IAI). These two interferences often occur simultaneously in mobile multiple-input multiple-output (MIMO)-orthogonal frequency division multiplexing (OFDM) communication systems. The IDL detector enhances ICI mitigation and avoids the notorious error propagation problem encountered in conventional interference mitigation/cancellation schemes. In addition, this study proposes three techniques to reduce the required computational complexity by 99.63% in complex additions, 99.69% in complex multiplications, and 67.25% in comparison operations. Simulation results confirm the theoretical upper bound and also show that the bit error rate performance of the receiver in high-mobility channels is comparable to that of a maximum-likelihood MIMO-OFDM receiver in stationary channels, i.e., the ICI-free scenario.

In this paper, we derive a closed-form expression for the probability density/mass function (PDF/PMF) and the moment generating function (MGF) of the quantized detector soft output, i.e., extrinsic log-likelihood ratio (LLR), for multiple-input multiple-output (MIMO) bit-interleaved coded modulation with iterative decoding (BICM-ID) systems. The effect of either LLR clipping or LLR clipping with rounding, often applied in practical implementations, are considered. Using the derived expression, we analyze the asymptotic coded bit error rate (BER) for MIMO BICM-ID systems with the two quantization operations under a flat Rayleigh fading channel. The error rate degradation caused by quantizing the extrinsic LLR is then interpreted as an additional signal-to-noise ratio (SNR) loss. Rather than Monte Carlo simulations, this theoretical treatment provides a more convenient alternative to determining the clipping level and optimal word-length (the number of bits needed to represent signals) for LLR in a BICM-ID implementation. Finally, several other applications of this proposed theoretical analysis are also demonstrated.

In this paper, we theoretically analyze the asymptotic coded bit error rate (BER) for multiple-input multiple-output bit-interleaved coded modulation (MIMO-BICM) with linear minimum mean-squared error (MMSE) detection and estimation for a flat Rayleigh fading channel. The numerical simulations validate the accuracy of our theoretical analysis. With such study, we can model the BER improvement of MMSE detection compared with zero-forcing detection as a signal-to-noise (SNR) gain.

This paper proposes a new concept of multiple-input multiple-output (MIMO) detection, aiming at minimizing the average computational cost. The detection methods are adapted according to the estimated channel state information to deliver just-acceptable error rate (JAER) performance. Error rate models for two popular MIMO detection algorithms are derived given the channel matrix. From these models, a channel-adaptive-MIMO (CA-MIMO) receiver with detector-switching strategies is proposed. Simulation results demonstrate that the proposed CA-MIMO detector meets the JAER criterion efficiently. Compared with the sophisticated Sphere Search (SS) MIMO detector, the average saving at moderate signal-to-noise ratio (SNR) is around 58% to 72%, depending on different modulation alphabets. At high SNR, the CA-MIMO detector almost always switch to Zero-Forcing (ZF) detection, where the complexity is several orders lower than the SS detector.

In mobile multiple-input multiple-output (MIMO) - orthogonal frequency division multiplexing (OFDM) communication systems, inter-carrier interference (ICI) and inter-antenna interference (IAI) are two crucial factors that can significantly affect detection performance. Conventionally, ICI and IAI are handled sequentially by ICI mitigation and MIMO detection. This paper proposes a novel iterative receiver where soft information, computed from a list of MIMO symbol vectors and associated ICI assumptions, is interchanged between the "ICI-aware" list-update MIMO detector and a forward error correction (FEC) decoder. Furthermore, by exploiting the difference between tentative ICI-inducing symbol vectors, we propose a low-complexity delta-ICI method for list update. Simulation results show that the proposed iterative MIMO-OFDM receiver in high-mobility channels can achieve similar detection performance as that of a MIMO-OFDM receiver in stationary (ICI-free) channels.

This paper proposes a novel solution to cross-layer optimization for streaming of image/video over adaptive MIMO-OFDM wireless networks. Joint source-channel coding (JSCC) that includes progressive coding and adaptive modulation/code set (MCS) is applied to a singular value decomposition (SVD)-based MIMO-OFDM transmission system. Armed with a packet error rate (PER) model that considers modulation, code rate and SNR, we present a novel resource allocation algorithm that determines the optimal set of parameters. Wireless transmission simulation indicates that the proposed design can deliver images at same level of PSNR with 3–5dB smaller required channel SNR than the conventional approach.

In this paper, we analyze the error rate degradation caused by the finite-precision extrinsic log-likelihood ratio (LLR), i.e., demapper output, for multiple-input multiple-output (MIMO) bit-interleaved coded modulation with iterative decoding (BICM-ID). A closed-form expression for the probability density function (pdf) of the metric difference with finite precision is derived. This pdf is well-approximated by two approaches, namely the pseudo quantization noise (PQN) model and the pdf tail truncation. Moreover, we interpret such performance degradation as an additional signal-to-noise ratio (SNR) loss. As validated by Monte Carlo simulations, this SNR loss can be directly applied at the first iteration, extending our analysis to non-iterative scenario. This work provides a convenient indicator for deciding the LLR precision in real implementations.

This paper introduces a new framework of the multiple-input multiple-output (MIMO) detection in iterative receivers. Unlike the conventional methods processing with symbol lattice, we consider the delta symbol lattice, i.e., the difference between two arbitrary points in the symbol lattice. The inherent flexible, symmetric, and sparse properties of the delta lattice enhance the detection in both complexity and performance aspects. Consequently, we propose a delta-list MIMO (DL-MIMO) detection which separately exploits the channel information and the a priori information so that a soft-input soft-output sphere decoder is dispensable. Simulation results demonstrate this hardware-friendly DL-MIMO detection delivers nearly-optimal performance at affordable cost in a practical scenario.

This paper presents a low-complexity interpolation-based channel estimator suited for scattered-pilot OFDM systems in fast-fading channel. The proposed estimator consists of two interpolators: one RLS interpolator for estimating scattered subcarriers along the time direction and another raised-cosine (RC) interpolator for estimating data subcarriers along the frequency direction. A low-complexity architecture tailored for DVB-T/H is demonstrated as an exemplar. Simulation results show that the proposed channel estimator has comparable accuracy with almost order-of-magnitude lower complexity than conventional adaptive channel estimators.

Using the Schnorr-Euchner (SE) order for soft-input sphere decoders is inefficient for implementation, because it requires exhaustive calculation and sorting of partial metrics of all constellation points. Instead, low-complexity methods can be applied by separating the partial metric into channel information and a priori information and solely enumerating based on one of them. With such an orthogonalization, this paper presents an algorithm that effectively combines these two enumerations to deliver an order close to the SE one. Mathematical analyses and simulation results demonstrate that this is the first algorithm allowing for a low-complexity implementation with optimal error rate performance for any number of iterations.

This paper proposes a new concept of multiple-input multiple-output (MIMO) detection, aiming at minimizing the average computational cost. The detection methods, according to the estimated channel state information, are adapted to deliver just acceptable error rate. Performance of two popular MIMO detectors is analyzed. Based on these analyses, a channel adaptive MIMO (CA-MIMO) receiver with a novel method- selection strategy is investigated. Simulation results demonstrate that the proposed CA-MIMO detector, operating at as low SNR as the sphere search does, achieves huge average complexity saving.

This paper presents circuit design of a low-power delay buffer. The proposed delay buffer uses several new techniques to reduce its power consumption. Since delay buffers are accessed sequentially, it adopts a ring-counter addressing scheme. In the ring counter, double-edge-triggered (DET) flip-flops are utilized to reduce the operating frequency by half and the C-element gated-clock strategy is proposed. A novel gated-clock-driver tree is then applied to further reduce the activity along the clock distribution network. Moreover, the gated-driver-tree idea is also employed in the input and output ports of the memory block to decrease their loading, thus saving even more power. Both simulation results and experimental results show great improvement in power consumption. A 256 times 8 delay buffer is fabricated and verified in 0.18 mum CMOS technology and it dissipates only 2.56 mW when operating at 135 MHz from 1.8-V supply voltage.

In this paper, we first show equivalence of OFDM channel estimation using time-domain windowing and using frequency-domain interpolation. Based on this equivalence, a new frequency-domain channel interpolator featuring the advantage of time-domain channel impulse response windowing is proposed. Furthermore, the proposed raised-cosine channel interpolator can adaptively adjust its coefficients to accommodate various channel power delay profiles. Both theoretical and simulation results verify that the proposed interpolator achieves more accurate channel estimation performance than other existing solutions.

In this paper, we derive the asymptotic bit error rate (BER) for multiple-input multiple-output bit-interleaved coded modulation (MIMO-BICM) with linear zero-forcing (ZF) receivers for a temporally correlated flat Rayleigh fading channel. Pilot symbol assisted modulation (PSAM) in combination with linear minimum mean-squared error (LMMSE) channel estimation is considered. We also demonstrate that the deterioration due to imperfect channel state information (CSI) can be represented by a signal-to-noise ratio (SNR) degradation.

OFDM systems suffer severe performance degradation in the presence of IQ imbalance and phase noise. This paper provides a new IQ imbalance estimation scheme that works under phase noise effect and multi-path channel with large delay spread. Furthermore, the proposed method can suppress the interference from neighboring subcarriers caused by phase noise. The proposed scheme significantly mitigates analog front-end impairments and eases their specifications, which in turn lowers the cost of OFDM transceivers.

In this correspondence, we analytically derive the bit error rate (BER) for bit-interleaved coded modulation (BICM) under the assumption of a temporally correlated flat Rayleigh fading channel. We assume the channel state information (CSI) to be unknown at receiver side and consider a linear minimum mean-squared error (LMMSE) channel estimator that relies on periodically inserted pilot symbols. We give asymptotic results for both non-iterative BICM and BICM with iterative decoding (BICM-ID). Furthermore, we show that the interpretation of the channel estimation error as an SNR degradation holds true in these cases.

This paper presents the algorithm and hardware implementation of a low hardware complexity Rayleigh faders designed for real-time baseband MIMO channel emulation. This novel Rayleigh fader model achieves extremely low hardware complexity through a new mathematical model and extensive hardware sharing.

This paper presents the implementation of a reconfigurable real-time digital baseband MIMO channel emulator with flexible user interface. The emulator implements several transceiver impairments and a wireless correlated MIMO channel with the help of a novel low-complexity Rayleigh fader design. The rich set of emulated effects and high emulation speed make the proposed system very useful in MIMO baseband transceiver development.

Rake receiving is a crucial technique in spread spectrum system. Typical rake receivers, implemented all-digitally, entail considerable power consumption. Though generally regarded as a promising low power solution, analog rake receivers have not been widely adopted because of formidable design complexity in integrating the overall analog and digital systems. In this paper, we present a practical scheme to realize a digitally-controlled mixed-signal rake receiver with both software and hardware simulation results demonstrating the efficiency of the proposed system. Synthesis and SPICE simulations using 0.18/spl mu/m CMOS technology show that the power consumption is less than 2.5 mW while operating at 16 MHz clock rate at 1.5 V supply voltage.

In this paper, based on the IEEE 802.11n proposal, a MIMO-OFDM baseband receiver design for next-generation WLAN is proposed. A MIMO-OFDM receiver with algorithms for timing and frequency synchronization and MIMO detection is designed and simulated. Moreover, the circuits for all functional blocks in the receiver are also designed. Functional simulation results demonstrate that the proposed receiver design is capable of high link throughput with efficient spectrum utilization and is suitable for the application of next-generation wireless LAN.

Orthogonal frequency-division multiplexing (OFDM) modulation provides a high data rate communication service. However, in mobile reception, a loss of sub-carrier orthogonality due to Doppler-spread leads to inter-carrier interference (ICI). This paper proposes a channel estimation scheme based on one-dimensional raised cosine interpolation. A time-domain raised cosine interpolation plus a frequency-domain raise cosine interpolator with adaptive roll-off factor can estimate the channel response very well in high-mobility environments.

As wireless communication services become more prevalent, bandwidth requirement increases dramatically. As such, the concept of cognitive radio (CR) has recently received much attention. In this paper, we present a MIMO-OFDM based CR system capable of dynamically adjusting its system parameters according to spectrum allocation. From system simulation, the proposed transceiver is shown to be a promising solution for CR applications.

The boundary-scan test provides a structural test solution for the densely packed digital electronics. For RF devices, the structural test also provides a good diagnostic resolution to the structural defects of RF circuits, especially for the high pin-count RF-SOCs. In this paper, the boundary-scan test is implemented on a 5-GHz RF pin using LC isolation networks to connect the RF lines and the boundary-scan cell, which isolates the RF circuitry from the digital boundary scan cell. This technique overcomes the parasitic loading problems and provides a minimum RF performance degradation to a RFIC. The measurement results show only 0.4-dB gain degradation in a 5-GHz amplifier with a boundary-scan cell and LC isolation networks.

This paper presents a new audio coder that includes two techniques to improve the sound quality of the audio coding system. First, a forward masking model is proposed. This model exploits adaptation of the peripheral sensory and neural elements in the auditory system, which is often deemed as the cause of forward masking. In the proposed audio coder, the forward masking is first modeled by a nonlinear analog circuit and then difference equations for finding the solution of this circuit are formulated. The parameters of the circuit are derived from several factors, including time difference between masker and maskee, masker level, masker frequency, and masker duration. Inclusion of this model in the coding process will remove more redundancy inaudible to humans and thus improves the coding efficiency. Secondly, we propose a new vector quantization technique, whose codebooks are generated by a perceptually weighted binary-tree self-organizing feature maps (PW-BTSOFM) algorithm. This vector quantization technique adopts a perceptually weighted error criterion to train and select codewords so that the quantization error is kept below the just-noticed distortion (JND) while using the smallest possible codebook, again reducing the required coded bit rate. Experimental objective and subjective sound quality measurements show that the proposed audio coding scheme requires about 30% less bits than the MPEG layer III audio coding standard.

We propose an analog integrated circuit to compute the motion field of a time-varying image by means of a multiple-constraint method. The chip converts optical input to an electrical form with an array of on-chip image sensors. A resistive network is used to smooth the input image. The spatial and temporal derivatives of the image are used to compute the optical-flow constraint. An array of motion cells enforce the optical-flow constraints, and two nonlinear resistive networks enforce the smoothness constraint over the optical-flow field. In order to preserve object boundaries, the smoothness constraint must be adjusted according to discontinuities in the optical-flow field and edges in the image. This is achieved by the nonlinear nature of the resistors and by adjusting the conductance of the resistors according to spatial gradients of image intensity. A 32/spl times/32 optical-flow based motion field detection chip is fabricated using a 0.5 /spl mu/m CMOS process. Measurement results show that the proposed IC can compute the optical-flow field in a scene efficiently and correctly so as to facilitate segmentation of moving objects in image sequences.

The paper presents a parametric module design framework that is suitable for datapath/DSP soft-IP design. This framework is based on the integration of various frequently used parametric module generators. Under this design framework, system or circuit designers specify the structural information of the modules in C++, and then compile and co-simulate with any C/C++ programs/algorithms. Furthermore, they can manually adjust the simulation model whenever necessary. Once the system design is completed, an efficient gate-level Verilog code can soon be generated automatically. By examining the system functionality using high-level language and automatically translating the design entries into gate-level description, we can easily keep our design effort at system level while maintaining a tight consistency between different levels of abstraction. Therefore the proposed framework yields a fast, robust, and cost-effective solution to high-complexity datapath/DSP module design.

This paper presents a new forward masking model for perceptual audio coding. This model exploits adaptation of the peripheral sensory and neural elements in the auditory system, which is often deemed as the cause of forward masking. Nonlinearity of the ear is modeled by a nonlinear analog circuit with difference equations. We incorporate this model in the MPEG layer III audio coding scheme and construct a masking plane in the frequency-time space. With some extra computations, the new audio coding scheme can improve the sound quality of the decoded audio signals. In our experiments, subjective and objective sound quality measurements show that, to achieve the same reconstructed sound quality, the new scheme requires 12% to 23% less bits than the original MPEG layer III scheme.

In this paper, an all-digital differentially encoded quaternary phase shift keying (DEQPSK) direct sequence spread-spectrum (DSSS) transceiver is proposed. It consists of two parts: a baseband/IF spread-spectrum transmitter and a coherent intermediate frequency (IF) receiver. The center frequency of this IF receiver is 11 MHz and the sampling rate is 44 Msamples/second. Modulation/demodulation, carrier recovery, PN code acquisition, and differential coding are all provided within a single chip. Functional optimization and architecture design have been done before layout implementation. Furthermore, we added testing circuits in this chip and thus each functional block is easily tested. The chip was fabricated through TSMC 0.8 /spl mu/m n-well CMOS SPDM technology. The maximum operational clock rate is measured at over 90 MHz (5 V, over 4 Mbps), and the minimum supply voltage for 2 Mbps (44 MHz) rated speed is 2.6 V.

A scalable implementation scheme for multirate finite impulse response (FIR) filters is presented in this paper. The implementation scheme can reduce the time and area cost of a multirate FIR filter simultaneously. According to the throughput requirement, the proposed scheme achieves a minimum-area design with specified speed. Furthermore, by employing the scalable implementation scheme, we also propose an efficient design technique for subband filter banks.

A novel and efficient block-matching motion estimation criterion called minimized maximum error (MiniMax) is considered. The proposed method can save hardware area about 15% with acceptable video performance. A chip which combines the MiniMax matching criterion and the one-dimensional full search algorithm is presented. The ASIC is motivated by the need of the intensive computational demand to perform motion estimation in real time. The proposed single chip can match the applications of H.261 and MPEG international standards. Chip cascading is allowed for larger searching range applications.>

We propose a modified fast algorithm for discrete cosine transform (DCT) by transferring the results from the discrete Hartley transform (DHT) to one additional CORDIC (coordinate rotation digital computer) computing stage. A fast CORDIC-based systolic array is designed with four derived attractive features, including: (1) the single/double data folding feature; (2) the constructive feature; (3) the to-computing feature; and (4) the redundant computation. Due to its properties, the proposed design has an efficient hardware utilization and a high throughput rate. By using the redundant path, this design also has the capability of error detection.>

In this paper, we propose a modified Malvar algorithm that can transfer the Discrete Hartley Transform (DHT) results to the Discrete Cosine Transform (DCT) by using a one additional CORDIC computing stage. A fast CORDIC-based systolic array is designed with four attractive features the single/double data folding feature; the constructive feature; the co-computing feature; and redundant path computation. Due to the existence of the redundant path, the proposed design also has the capability of error detection.>

This paper describes fully pipelined parallel architectures for the 3-step search block-matching motion estimation algorithm. Difficulties of this algorithm in hardware implementation were overcome by use of intelligent data arrangement and memory configuration. Techniques for reducing interconnections and external memory accesses were also developed. Because of their low costs, high speeds, and low memory bandwidth requirements, the proposed architectures provide efficient solutions for real-time motion estimations required by various video applications.>

A tree-structure based architecture for vector quantization (VQ) is proposed and implemented by VLSI in this paper, The proposed folded-tree architecture is designed by 0.8 /spl mu/m CMOS VLSI technology. The die size is 4.65/spl times/5.21 mm/sup 2/ and estimated clock rate is about 34 MHz, which satisfies most real-time applications. Since it is basically a mean squared error computation circuit, various kinds of VQ algorithms can apply on the proposed architecture.>

In this paper, we propose a binary-tree structure neural network model suitable for structured clustering. During and after training, the centroids of the clusters in this model always form a binary tree in the input pattern space. This model is used to design tree search vector quantization codebooks for image coding. Simulation results show that the acquired codebook not only produces better-quality images but also achieves a higher compression ratio than conventional tree search vector quantization. When source coding is applied after VQ, the new model performs better than the generalized Lloyd algorithm in terms of distortion, bits per pixel, and encoding complexity for low-detail and medium-detail images.>

A new hardware-oriented algorithm called the one-dimensional full search (1DFS) is presented for block-matching motion estimation in video compression. The simulation for this algorithm follows H.261 and MPEG international standards. In MPEG simulation, structures with 1-, 2- and 3-frame interpolation are compared. The performance of 1DFS is superior to that of other fast search algorithms. And it has more regular data flow, data reuse and less control overhead. It is an alternative for 2D full search block matching and achieves a good compromise between computational complexity and performance. With competent performance and reasonable computation complexity, the proposed method is more suitable for real-time hardware realization of a VLSI motion estimator for video applications.>

Proposes three modifications on the 3-step hierarchical search for video coding: the multiple-candidate search that improves the estimation accuracy, a method of subsampling that reduces computation and input data amount, and an overlapping strategy to improve the accuracy of a large-area search. Experimental results show that combining these techniques provides high-speed and high-precision motion estimators with reduced on-chip buffers and lower input bandwidth requirements.>

The paper describes fully pipelined parallel architectures for the 3-step hierarchical search block-matching algorithm, a fast motion estimation algorithm for video coding. The advantage of this algorithm was completely utilized by use of intelligent data arrangement and memory configuration. Techniques for reducing interconnections and external memory accesses were also developed. Because of their low costs, high speeds, and low memory bandwidth requirements, the proposed 3-PE, 9-PE, and 27-PE architectures provide efficient solutions for real-time motion estimations required by video applications of various data rates, from low bit-rate video to HDTV systems.>

A multivalued neural associative memory model based on a recurrent network structure is proposed. This model adopts the same principle proposed in the authors' previous work, the exponential correlation associative memories (ECAM). The model also has a very high storage capacity and strong error-correction capability. The major components of the new model include a weighted average process and some similarity-measure computation. As in ECAM, in order to enhance the differences among the weights and make the largest weights more overwhelming, the new model incorporates a nonlinear function in the calculation of weights. Several possible similarity measures suitable for this model are suggested. Simulation results of the performance of the new model with different measures show that, loaded with 500 64-component patterns, the model can sustain noise with power about one fifth to three fifths of the average signal power.

An efficient block matching algorithm (BMA) for motion estimation is presented. This BMA exploits motion correlation of neighbor blocks in the temporal direction to reduce the search area. Instead of finding the 2D motion vector directly, this BMA finds two 1D displacements in parallel on two axes independently within the reduced search area. Simulation results show that this algorithm can rival conventional BMAs for performance. The hardware-oriented features of this BMA guarantee that it is more suitable for the hardware realization of a VLSI motion estimator.>

The authors present an efficient block-matching algorithm called the parallel hierarchical one-dimensional search (PHODS) for motion estimation. Instead of finding the two-dimensional motion vector directly, the PHODS finds two one-dimensional displacements in parallel on the two axes (say x and y) independently within the search area. The major feature of this algorithm is that its search speed for the motion vector is faster than that of the other search algorithms on account of its simpler computations and parallelism. Compared with previous research in terms of four measurements, the PHODS can rival those algorithms for performance. The hardware-oriented features of the PHODS, i.e., regularity, simplicity, and parallelism, guarantee that the PHODS is more suitable for hardware realization of a VLSI motion estimator.>

A model for a class of high-capacity associative memories is presented. Since they are based on two-layer recurrent neural networks and their operations depend on the correlation measure, these associative memories are called recurrent correlation associative memories (RCAMs). The RCAMs are shown to be asymptotically stable in both synchronous and asynchronous (sequential) update modes as long as their weighting functions are continuous and monotone nondecreasing. In particular, a high-capacity RCAM named the exponential correlation associative memory (ECAM) is proposed. The asymptotic storage capacity of the ECAM scales exponentially with the length of memory patterns, and it meets the ultimate upper bound for the capacity of associative memories. The asymptotic storage capacity of the ECAM with limited dynamic range in its exponentiation nodes is found to be proportional to that dynamic range. Design and fabrication of a 3-mm CMOS ECAM chip is reported. The prototype chip can store 32 24-bit memory patterns, and its speed is higher than one associative recall operation every 3 mus. An application of the ECAM chip to vector quantization is also described.