Simulation is still one of the most important subtasks when designing a VLSI circuit. However more and more elements on a chip increase simulation runtimes. Especially on transistor level with highly accurate element modelling, long simulation runtimes of typically several hours delay the design process. One possibility to reduce these runtimes is to divide the circuit into several partitions and to simulate the partitions in parallel. But the success of such a parallel simulation is heavily dependent on the quality of the partitioning. This paper presents a new approach for partitioning VLSI circuits on transistor level and gives runtimes of parallel simulations of large industrial circuits. The resulting runtimes show considerable improvement compared to a known partitioning method, the node tearing method.

Article Free Access Share on Java driven codesign and prototyping of networked embedded systems Authors: Josef Fleischmann Technical University of Munich, Inst. of Electronic Design Automation, D-80290 Munich, Germany Technical University of Munich, Inst. of Electronic Design Automation, D-80290 Munich, GermanyView Profile , Klaus Buchenrieder Siemens AG, Corporate Technology, D-81730 Munich, Germany Siemens AG, Corporate Technology, D-81730 Munich, GermanyView Profile , Rainer Kress Siemens AG, Corporate Technology, D-81730 Munich, Germany Siemens AG, Corporate Technology, D-81730 Munich, GermanyView Profile Authors Info & Claims DAC '99: Proceedings of the 36th annual ACM/IEEE Design Automation ConferenceJune 1999 Pages 794–797https://doi.org/10.1145/309847.310068Published:01 June 1999Publication History 7citation356DownloadsMetricsTotal Citations7Total Downloads356Last 12 Months5Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

In the design of embedded hardware/software systems, exploration and synthesis of different design alternatives and co-verification of specific implementations are the most demanding tasks. Networked embedded systems pose a new challenge to existing design methodologies as novel requirements like adaptivity and runtime-reconfigurability arise. In this paper; we introduce a co-design environment based on the Java language which supports specification, co-synthesis and prototype execution for dynamically reconfigurable hardware/software systems.

In a VHDL-based design flow for application specific integrated circuits, VITAL provides a uniform methodology for developing ASIC libraries for signoff simulation. The VITAL Standard includes specialized routines for describing behavior and timing of ASIC cells and integrates back-annotation via Standard Delay Format (SDF). One of the key issues of the VITAL initiative was to accelerate simulation performance at gate level by allowing only a restricted set of VHDL. In this paper, we present an efficient implementation of the VITAL-Standard in our object-oriented, event-driven logic simulation tool OLIVIA. First promising results concerning simulation performance compared to conventional VHDL-Simulators are given.