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C. C. Su

dblp:67/6749 · DBLP profile ↗
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4ranked-venue papers
3as first author
0since 2021 · last 2007
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 3 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 92% Integrated circuit design · 8%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
logic synthesis
0.011968
Unitary Shift-Register Realizations of Sequential Machines · IEEE Trans. Computers 1968
Electronic design automation › logic synthesis
sequential circuit synthesis
0.011968
Unitary Shift-Register Realizations of Sequential Machines · IEEE Trans. Computers 1968
Electronic design automation › logic synthesis
state assignment
0.011968
Unitary Shift-Register Realizations of Sequential Machines · IEEE Trans. Computers 1968
Integrated circuit design
digital circuit design
0.011968
Unitary Shift-Register Realizations of Sequential Machines · IEEE Trans. Computers 1968
Electronic design automation › logic synthesis › sequential circuit synthesis
shift-register realization
0.011968
Unitary Shift-Register Realizations of Sequential Machines · IEEE Trans. Computers 1968

Methods — techniques the papers use, named apart from their topics

state assignment algorithm · 0.0
YearPublicationVenuePosition
2007 Guest Editorial
Marcelo Lubaszewski, Andrew Richardson 0001, C. C. Su
J. Electron. Test.3
2004 Dynamic Analog Testing via ATE Digital Test Channels
abstract
A dynamic analog test methodology using digital tester is proposed. A simple triangular waveform is built on the device interface board for the stimulus generation. The response waveform is quantized by the dual comparators in a digital pin electronic circuit. Statistical analysis is conducted to enhance the quantization resolution and minimize the noise effect. The experimental results using an ATE show that the error is less than 2%. It confirms the feasibility of the proposed methodology.
C. C. Su, H. W. Huang, D. S. Tu, C. L. Lee, Jerry C. H. Lin
Asian Test Symposium1
1990 Optimal gate-matrix layout of CMOS functional cells
C. C. Su, Majid Sarrafzadeh
Integr.1
1968 Unitary Shift-Register Realizations of Sequential Machines
abstract
Abstract—The problem of determining secondary state assignments for sequential machines such that the binary memory elements are connected in the form of shift registers is studied. An algorithm for finding such state assignments is developed. One or more code words may be assigned to a state of the sequential machine. The only restriction is that the realizations be unitary. A single shift-register realization of a sequential machine is unitary if and only if all the code words assigned to a state have the same first digits. A multiple shift-register realization of a sequential machine is unitary if and only if all the code words assigned to a state have l identical digits, where l is the number of shift registers in the realization. With our technique, the unitary realizations with the minimum number of shift registers can be obtained for any finite, deterministic, synchronous, and reduced (minimal-state) sequential machine, each of whose states has a nonempty predecessor set. The algorithm is suitable for programming on digital computers.
C. C. Su, Stephen S. Yau
IEEE Trans. Computers1