This paper presents a digital-to-analog converter (DAC) sharing method for time-interleaved (TI)-incremental delta-sigma modulators (I-ΔΣMs), which allows significant savings of passives by 40 % in the DACs. The proposed DAC sharing shows an increased robustness to nonlinearities and is further adapted to a linearization technique known from non-TI-I-ΔΣMs. The paper extends the known linearization technique to achieve optimal signal to noise and distortion ratio (SNDR) across the modulator’s entire dynamic range (DR). An increase of 7 dB in SNDR is demonstrated for low input signals powers, which has not been shown before. It is demonstrated, that the high linearity of the system allows to compensate for the gain mismatch in TI operation with a simple gain factor to retain near ideal performance. Furthermore, the paper proposes a practical circuit implementation for the shared DAC and a correlation based error estimation to determine the channel gain mismatch.

This paper presents a new architecture as well as a compensation method for discrete-time (DT) noise-canceling SMASH (NC-SMASH) bandpass delta-sigma modula-tors$(\mathbf{BP}-\Delta\Sigma \mathbf{Ms})$. The proposed method relaxes timing constraints on the feedback path by one clock cycle, which in turn relaxes the timing constraints on the adder in front of the quantizer, and the digital adder for the SMASH architecture. In SMASH architectures, this relaxed timing enables an NC analog-to-digital converter (ADC) architecture. Unlike state-of-the-art solutions, which require an analog unit delay at the ADC's input to achieve these relaxed requirements, the presented bandpass approach renders this analog delay and the respective input capacitor unnecessary. In a respective circuit implementation this significantly reduces the area and power consumption. The proposed compensation method allows the designer to choose between a non-delayed input and an elimination of the input signal component inside the loop filter, which would require a delayed input path.

Fast switching power supplies allow to reduce the size and cost of external passive components. However, the capacitive switching losses of the power stage will increase and become the dominant part of the total losses. Therefore, resonant topologies are the known key to reduce the losses of the power stage. A power switch with an additional resonant circuit can be turned on under soft-switching conditions, ideally with zero-voltage-switching (ZVS). As conventional resonant converts are only efficient for a constant load, this paper presents a predictive regulation loop to approach soft-switching conditions under varying load and component tolerances. A sample and hold based detection circuit is utilized to control the turn-on of the power switch by a digital regulation. The proposed design was fabricated in a 180 nm high-voltage BiCMOS technology. The efficiency of the converter was measured to be increased by up to 16 % vs. worst case timing and by 13 % compared to a conventional hard-switching buck converter at 20 V input voltage and at approximately 8 MHz switching frequency.

An authentic mode-toggled detector (AMTD) technique is proposed to achieve load and line regulations in a proposed buck-boost (BB) converter. In the case of load transient, conventional BB converter will oscillate and cannot settle to a wellregulated output voltage owing to the on-resistance of the power MOSFETs. Accurate and expeditious mode-toggled detection in the BB converter meet the requirements of load and line transient response by means of the proposed adaptively near-immediate freezer (ANIF) technique. Besides, due to pulse frequency modulation (PFM) implemented in the proposed BB converter, ultra wide load range from 10mA to 900mA can have high efficiency from 80% to 95%. Simulation results show the proposed BB converter fabricated in VIS 0.25μm process can be wellregulated under the input voltage ranging from 2.7V to 4.2V.

The charge pump belongs to the most critical blocks for electromagnetic compatibility (EMC) of low dropout linear regulators (LDO) because of its switching nature. The goal of this paper is to contribute charge pump design practice and a prediction method for the LDO EMC performance already in an early design phase. LDO noise coupling mechanisms are analyzed. EMC aware circuit design includes the choice of low noise architectures, the right switching frequency and noise filtering. The derived simulation method shows very good matching with EMC test results for an LDO with two different charge pumps fabricated in 350nm high-voltage BiCMOS technology. For a realistic prediction of the EMC noise magnitude, a relatively simple simulation setup gives results with <;3dBμV accuracy. A trippler current mode charge pump turned out to be well suitable for EMC. Conducted emissions could be predicted and confirmed to be improved by ~50dBμV versus a conventional voltage mode charge pump.