In various areas of life, rechargeable lithium-ion batteries are the technology of choice. Equivalent circuit models are utilized extensively in characterizing and modeling energy storage systems. In real-time applications, several generic-based battery models are created to simulate the battery’s charging and discharging behavior more accurately. In this work, we present two generic battery models based on Mittag-Leffler function using a generic Standard battery model as a reference. These models are intended to fit the continuous discharging cycles of lithium-ion, Nickel-cadmium, and Nickel-metal hydride batteries, as well as one set from the NASA randomized battery usage dataset. We formulate the parameter identification as an optimization problem, solved with Marine Predator Algorithm. The optimized models show very good matching against the measured data.

Abstract Stochastic computing is a relatively new approach to computing that has gained interest in recent years due to its potential for low-power and high-noise environments. It is a method of computing that uses probability to represent and manipulate data, therefore it has applications in areas such as signal processing, machine learning, and cryptography. Stochastic steganography involves hiding a message within a cover image using a statistical model. Unlike traditional steganography techniques that use deterministic algorithms to embed the message, stochastic steganography uses a probabilistic approach to hide the message in a way that makes it difficult for an adversary to detect. Due to this error robustness and large bit streams stochastic computing, they are well suited for high capacity and secure image steganography. In this paper, as per the authors’ best knowledge, image steganography using stochastic computing based on linear feedback shift register (LFSR) is proposed for the first time. In the proposed technique, the cover image is converted to stochastic representation instead of the binary one, and then a secret image is embedded in it. The resulting stego image has a high PSNR value transmitted with no visual trace of the hidden image. The final results are stego image with PSNR starting from 30 dB and a maximum payload up to 40 bits per pixel (bpp) with an effective payload up to 28 bpp. The proposed method achieves high security and high capability of the number of stored bits in each pixel. Thus, the proposed method can prove a vital solution for high capacity and secure image steganography, which can then be extended to other types of steganography.

Hardware accelerators outperform CPUs in terms of performance by parallelizing the algorithm architecture and using the device’s programmable resources. FPGA is a type of hardware accelerator that excels not only in performance but also in energy efficiency. So, it provides a suitable platform for implementing complicated fractional-order systems. This paper proposes a novel phase-based optimization method to implement fractional operators using FIR and IIR filters. We also compare five fractional operator implementation methods on FPGA regarding resource utilization, execution time, power, and accuracy. These methods and the proposed one are evaluated in terms of power consumption, delay, and resources to assist the designer in determining the most suitable implementation method for the given application. The proposed method has a lower phase error of 14.7% in the case of derivative operation and a lower phase error of 18.83% in the case of integration compared to the literature. In addition, the proposed methods decreased the consumed power and area by more than three times compared to the fixed-window GL fractional operator. The proposed approach implements Heaviside’s inductor-terminated lossy line. In addition, it is employed as an edge detection kernel to demonstrate its effectiveness in image processing applications.

Coordinate Rotation Digital Computer (CORDIC) is a robust iterative algorithm that computes many transcendental mathematical functions. This paper proposes a reconfigurable CORDIC hardware design and FPGA realization that includes all possible configurations of the CORDIC algorithm. The proposed architecture is introduced in two approaches: multiplier-less and single multiplier approaches, each with its advantages. Compared to recent related works, the proposed implementation overpasses them in the included number of configurations. Additionally, it demonstrates efficient hardware utilization and suitability for potential applications. Furthermore, the proposed design is applied to a memristive chaotic system with different transcendental functions computed using the proposed reconfigurable block. The memristive system design is realized on the Artix-7 FPGA board, yielding throughputs of 0.4483 and 0.3972 Gbit/s for the two approaches of reconfigurable CORDIC.

A new second-order MOS transistor based circuit block approximating the behavior of a fractional-order capacitor is proposed. The circuit is modular and therefore the order of the approximation can be increased by more stages of the same circuit in cascade or in parallel. Simulation results using a TSMC 65nm CMOS technology are provided and show less than 2° of phase error in two decades around the center frequency of the approximation. Experimental results of realized fractional-order capacitors and of a fractional-order relaxation oscillator are also shown.

Area and power consumption are the main challenges in Network on Chip (NoC). Indeed, First Input First Output (FIFO) memory is the key element in NoC. Increasing the FIFO depth, produces an increas in the performance of NoC but at the cost of area and power consumption. This paper proposes a new hybrid CMOS-Memristor based FIFO architecture that consumes low power and has a small size compared to the conventional CMOS-based FIFOs. The predicted area is approximately equal to the half of that wasted in conventional FIFOs. The implementation of FIFO controller module is implemented using HDL. Moreover, the functionality test and the simulation results of the proposed architecture are presented. Simulation is done using ISF Xilinix and Cadence tools.

Recently, double pinch-off points have been discovered in some memristive devices where the I-V hysteresis curve intersects in two points generating triple lobes. This paper investigates a fractional-order flux-controlled mathematical model which is able to develop the multiple pinch-off points or multiple lobes. The conditions for observing double pinch-off points (triple lobes) are derived in addition to the locations of the pinch-off points which do not appear in the integer domain. Also, expressions for maximum and minimum conductance are derived. Finally, a floating fractional flux-controlled memristor emulator circuit to generate the triple lobes is introduced and discussed. The PSICE results and the mathematical model results are matched.

This paper proposes new multi-scrolls chaotic systems which is called the X-shape. The purpose is to have more complex systems and flexible ranges of the chaotic behavior. The proposed X-shape is a combination between V-shape and Λ-shape. This paper also represents the Heart-shape which considered a special case of the X-shape. The system complexity has been measured by MLE and compared with V-shape system. It shows lager MLE on the side of X-shape. In addition, the effect of changing system parameters has been discussed and compared with V-shape. Finally, a fully hardware implantation on FPGA has been proposed using Nexys 4 Artix-7 FPGA XC7A100T with optimum resources and the experimental results are provided.

This paper introduces a novel 2T2M memristor based memory cell which, offers higher stability and noise margins than previous works. The proposed 2T2M RRAM module is similar to conventional 6T SRAM module in terms of delay and number of interface pins. However, the predicted area of the proposed 2T2M RRAM cell is significantly lower compared to the CMOS based 6T SRAM cell, and is also expected to consume lower energy. The nonvolatile characteristics of the cell make it more attractive for nonvolatile random access memory design. Write, read and repeated read operations of the proposed 2T2M RRAM cell are briefly explained. A complete RRAM module array based on the proposed 2T2M cell is designed, and the schematic details of the IO circuit is shown. A comparison between the proposed 2T2M cell and previous works is presented.

This study introduces a novel image encryption system based on diffusion and confusion processes in which the image information is hidden inside the complex details of fractal images. A simplified encryption technique is, first, presented using a single‐fractal image and statistical analysis is performed. A general encryption system utilising multiple fractal images is, then, introduced to improve the performance and increase the encryption key up to hundreds of bits. This improvement is achieved through several parameters: feedback delay, multiplexing and independent horizontal or vertical shifts. The effect of each parameter is studied separately and, then, they are combined to illustrate their influence on the encryption quality. The encryption quality is evaluated using different analysis techniques such as correlation coefficients, differential attack measures, histogram distributions, key sensitivity analysis and the National Institute of Standards and Technology (NIST) statistical test suite. The obtained results show great potential compared to other techniques.

This study presents hardware realisation of chaos‐based stream cipher utilised for image encryption applications. A third‐order chaotic system with signum non‐linearity is implemented and a new post processing technique is proposed to eliminate the bias from the original chaotic sequence. The proposed stream cipher utilises the processed chaotic output to mask and diffuse input pixels through several stages of XORing and bit permutations. The performance of the cipher is tested with several input images and compared with previously reported systems showing superior security and higher hardware efficiency. The system is experimentally verified on XilinxVirtex 4 field programmable gate array (FPGA) achieving small area utilisation and a throughput of 3.62 Gb/s.