While cloud computing has provided major benefits by maximizing the use of resources within a cloud, the current solutions still face many challenges. In this paper, we propose performance enhancements for cloud computations, provided by integrating hardware acceleration into the computation services. We extend the Hadoop framework by adding provisions for hardware acceleration using Field Programmable Gate Arrays (FPGAs). Hardware acceleration using energy efficient FPGAs is used as a service within the clouds or to offload computations when needed. It can provide additional sources of revenues, reduced operating costs, and increased resource utilization. We developed a custom Hadoop system and tested four applications commonly used for machine learning and deep learning. The results show the benefits of hardware acceleration and the high performance gains in smaller execution times and energy consumption.

In this article, we propose new extensions to Hadoop to enable clusters of reconfigurable active solid-state drives (RASSDs) to process streaming data from SSDs using FPGAs. We also develop an analytical model to estimate the performance of RASSD clusters running under Hadoop. Using the Hadoop RASSD platform and network simulators, we validate our design and demonstrate its impact on performance for different workloads taken from Stanford's Phoenix MapReduce project. Our results show that for a hardware acceleration factor of 20×, compute-intensive workloads processing 153MB of data can run up to 11× faster than a standard Hadoop cluster.

High-performance superscalar architectures used to exploit instruction level parallelism in single-thread applications have become too complex and power hungry for the multicore processors era. We propose a new architecture that uses multiple small latency-tolerant out-of-order cores to improve single-thread performance. Improving single-thread performance with multiple small out-of-order cores allows designers to place more of these cores on the same die. Consequently, emerging highly parallel applications can take full advantage of the multicore parallel hardware without sacrificing performance of inherently serial and hard to parallelize applications. Our architecture combines speculative multithreading (SpMT) with checkpoint recovery and continual flow pipeline architectures. It splits single-thread program execution into disjoint control and data threads that execute concurrently on multiple cooperating small and latency-tolerant out-of-order cores. Hence we call this style of execution Disjoint Out-of-Order Execution (DOE). DOE uses latency tolerance to overcome performance issues of SpMT caused by interthread data dependences. To evaluate this architecture, we have developed a microarchitecture performance model of DOE based on PTLSim, a simulation infrastructure of the x86 instruction set architecture. We evaluate the potential performance of DOE processor architecture using a simple heuristic to fork control independent threads in hardware at the target addresses of future procedure return instructions. Using applications from SpecInt 2000, we study DOE under ideal as well as realistic architectural constraints. We discuss the performance impact of key DOE architecture and application variables such as number of cores, interthread data dependences, intercore data communication delay, buffers capacity, and branch mispredictions. Without any DOE specific compiler optimizations, our results show that DOE outperforms conventional SpMT architectures by 15%, on average. We also show that DOE with four small cores can perform on average equally well to a large superscalar core, consuming about the same power. Most importantly, DOE improves throughput performance by a significant amount over a large superscalar core, up to 2.5 times, when running multitasking applications.

In this paper, we propose to combine active solid state drives and reconfigurable FPGAs into a storage-compute node to use as a building block in a distributed, high performance computation platform for data intensive applications. We propose a complete framework for middleware functionality through an API abstraction layer that hides the complexity of accessing and processing data stored on these distributed nodes, thus allowing programmers to focus on the application, and not the underlying specialized architecture. The application in turn is re-architected to maximize its performance by delegating selected computations down to the storage-compute node. We present preliminary results measured on a real hardware prototype of a single-node. These results show that our proposed architecture provides more than a 2× improvement in performance over non-reconfigurable active-disk architectures that use electromechanical disks for storage and a 6× improvement in performance over a platform that performs the computation on the middle server.

Since the introduction of the first industrial out-of-order superscalar processors in the 1990s, instruction buffers and cache sizes have kept increasing with every new generation of out-of-order cores. The motivation behind this continuous evolution has been performance of single-thread applications. Performance gains from larger instruction buffers and caches come at the expense of area, power, and complexity. We show that this is not the most energy efficient way to achieve performance. Instead, sizing the instruction buffers to the minimum size necessary for the common case of L1 data cache hits and using new latency-tolerant microarchitecture to handle loads that miss the L1 data cache, improves execution time and energy consumption on SpecCPU 2000 benchmarks by an average of 10% and 12% respectively, compared to a large superscalar baseline. Our non-blocking architecture outperforms other latency tolerant architectures, such as Continual Flow Pipelines, by up to 15% on the same SpecCPU 2000 benchmarks.