Wafer map defect pattern recognition is critical to detect systemic process issues and improve yield. Machine-Learning (ML) techniques have recently been applied to automate the wafer map pattern recognition problem. However, as manually annotating wafer map data is expensive and time-consuming, most of the research work leverage on public available dataset such as WM-811K with known probe technology agnostic labels. Probe technology specific wafer map patterns, especially multisite probe touchdown related patterns, have not been considered, as they are affected by specific wafer test methodology and require customized labeled data which are not readily available. In this paper, we propose a synthetic data augmented training method to enable automated wafer map recognition for multisite probe specific patterns.

Accurate prediction of chip performance is critical for ensuring energy efficiency and reliability in semiconductor manufacturing. However, developing minimum operating voltage (Vmin) prediction models at advanced technology nodes is challenging due to limited training data and the complex relationship between process variations and Vmin. To address these issues, we propose a novel transfer learning framework that leverages abundant legacy data from the 16nm technology node to enable accurate Vminprediction at the advanced 5nm node. A key innovation of our approach is the integration of input features derived from on-chip silicon odometer sensor data, which provide fine-grained characterization of localized process variations—an essential factor at the 5nm node—resulting in significantly improved prediction accuracy.

Predicting the minimum operating voltage (Vmin) of chips stands as a crucial technique in enhancing the speed and reliability of manufacturing testing flow. However, existing Vminprediction methods often overlook various sources of variations in both training and deployment phases. Notably, overlooking wafer zone-to-zone (intra-wafer) variations and wafer-to-wafer (inter-wafer) variations diminishes the accuracy, data efficiency, and reliability of Vminpredictors. To address this challenge, we propose Restricted Bias Alignment (RBA), a novel data-efficient Vminprediction framework that introduces a variation alignment technique to simultaneously estimate inter- and intra-wafer variations. Furthermore, we propose utilizing class probe data to model inter-wafer variations for the first time.

The increasing complexity of electronic systems in autonomous electric vehicles necessitates robust methods for forecasting the degradation of critical components such as printed circuit boards (PCBs). Various time series forecasting methods have been investigated to predict in-situ resistance degradation under vibration loads. However, these methods failed to capture the degradation trend under strong measurement noise. This paper introduces Monotonic Segmented Linear Regression (MSLR), a novel approach designed to capture monotonic degradation trends in time series data under significant measurement noise. By incorporating monotonic constraints, MSLR effectively models the non-decreasing behavior characteristic of degradation processes. To further enhance reliability of the prediction, we integrate Adaptive Conformal Inference (ACI) with MSLR, enabling the estimation of statistically valid upper bounds for resistance degradation with high confidence. Extensive experiments demonstrate that MSLR outperforms state-of-the-art time series forecasting baselines on real-world PCB degradation datasets.

Accurate minimum operating voltage (Vmin) prediction is a critical element in manufacturing tests. Conventional methods lack coverage guarantees in interval predictions. Conformal Prediction (CP), a distribution-free machine learning approach, excels in providing rigorous coverage guarantees for interval predictions. However, standard CP predictors may fail due to a lack of knowledge of process variations. We address this challenge by providing principled conformalized interval prediction in the presence of process variations with high data efficiency, where the data from a few additional chips is utilized for calibration. We demonstrate the superiority of the proposed method on industrial 16nm chip data.

Predicting the minimum operating voltage$V_{min}$of chips is one of the important techniques for improving the manufacturing testing flow, as well as ensuring the long-term reliability and safety of in-field systems. Current$V_{min}$prediction methods often provide only point estimates, necessitating additional techniques for constructing prediction confidence intervals to cover uncertainties caused by different sources of variations. While some existing techniques offer region predictions, but they rely on certain distributional assumptions and/or provide no coverage guarantees. In response to these limitations, we propose a novel distribution-free$V_{min}$interval estimation methodology possessing a theoretical guarantee of coverage. Our approach leverages conformalized quantile regression and on-chip monitors to generate reliable prediction intervals. We demonstrate the effectiveness of the proposed method on an industrial 5nm automotive chip dataset. Moreover, we show that the use of on-chip monitors can reduce the interval length significantly for$V_{min}$prediction.

The stringent reliability requirements of electronic packages for safety-critical automotive applications have spurred developments in real-time monitoring of electronic components. A key aspect of these advancements is the availability of physical health sensing elements and failure-predicting algorithms that can be embedded within the integrated circuit. In this paper, 4-wire resistance measurement features are embedded in Quad-flat no-leads (QFN) packages to detect physical damages at the printed circuit board (PCB)-solder interconnect interface. Additionally, several Artificial Intelligent (AI) algorithms are assessed, and the most suitable one is implemented to predict the in-situ resistance changes over time under vibration loads. The time series failure forecast from this algorithm correlates well to the experimentally determined lifetime of solder joints. This method opens avenues for investigating the physics of degradation in board level reliability.

Determining the minimum operating voltage ($V_{min}$) of chip designs is critical for low power dissipation and assurance of quality and functional safety during manufacturing tests and in-field monitoring. We demonstrate how on-chip monitor data can be leveraged to provide accurate minimum operating voltage prediction using a domain-specific machine learning approach. Given limited measured chip data, the key challenge in developing a machine learning approach is to provide an accurate prediction while addressing overfitting and selecting a subset of optimal features. To this end, we propose to utilize a novel monotonic lattice neural network architecture that is geared towards accurate prediction by imposing domain-specific monotonic relationships between the input sensor data and$V_{min}$. Furthermore, we perform an effective feature selection by considering both the correlation between each feature and$V_{min}$as well as the co-linearity between the features. Experiments demonstrate superior performance in comparison with linear regression and conventional neural networks.

We discuss methods for fast spatiotemporal smoothing of calcium signals in dendritic trees, given single-trial, spatially localized imaging data obtained via multi-photon microscopy. By analyzing the dynamics of calcium binding to probe molecules and the effects of the imaging procedure, we show that calcium concentration can be estimated up to an affine transformation, i.e., an additive and multiplicative constant. To obtain a full spatiotemporal estimate, we model calcium dynamics within the cell using a functional approach. The evolution of calcium concentration is represented through a smaller set of hidden variables that incorporate fast transients due to backpropagating action potentials (bAPs), or other forms of stimulation. Because of the resulting state space structure, inference can be done in linear time using forward-backward maximum-a-posteriori methods. Non-negativity constraints on the calcium concentration can also be incorporated using a log-barrier method that does not affect the computational scaling. Moreover, by exploiting the neuronal tree structure we show that the cost of the algorithm is also linear in the size of the dendritic tree, making the approach applicable to arbitrarily large trees. We apply this algorithm to data obtained from hippocampal CA1 pyramidal cells with experimentally evoked bAPs, some of which were paired with excitatory postsynaptic potentials (EPSPs). The algorithm recovers the timing of the bAPs and provides an estimate of the induced calcium transient throughout the tree. The proposed methods could be used to further understand the interplay between bAPs and EPSPs in synaptic strength modification. More generally, this approach allows us to infer the concentration on intracellular calcium across the dendritic tree from noisy observations at a discrete set of points in space.

As mobile technologies evolved, the mobile networks provided users not only high mobility, but also high data rates and flexible services. Meanwhile, Internet services had been very successful from 1970s to date. However, the Internet and the mobile telecommunications evolved separately and were not compatible until 3GPP proposed the IP Multimedia Subsystem (IMS). In this paper, we first introduce mobile Web 2.0 application creation in the next generation IMS network. Then we propose a proof-of-concept service called “JoinMe” on the IBM-NCTU IMS network to study how a social networking service can be created for mobile networks.