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Yang Chai

dblp:68/10514 · DBLP profile ↗
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5ranked-venue papers
1as first author
4since 2021 · last 2026
—ORCID · conflict

Domains — the database's venue-derived domains; a paper can count in several

Applied, interdisciplinary, general and emerging computing · 2 · 2 since 2021Artificial intelligence and machine learning · 1 · 1 since 2021Systems, architecture and hardware · 1 · 1 first-authorComputer networks · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Integrated circuit design · 72% Emerging computing paradigms · 28%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
emerging device technologies
0.812024
Two-dimensional materials for future information technology: status and prospects · Sci. China Inf. Sci. 2024
Integrated circuit design › semiconductor devices › semiconductor device design
transistor design
0.812024
Two-dimensional materials for future information technology: status and prospects · Sci. China Inf. Sci. 2024
Emerging computing paradigms
neuromorphic computing
0.612022
Neuromorphic sensory computing · Sci. China Inf. Sci. 2022
Integrated circuit design
heterogeneous integration
0.212024
Two-dimensional materials for future information technology: status and prospects · Sci. China Inf. Sci. 2024
Integrated circuit design › 3d integration
monolithic 3d integration
0.212024
Two-dimensional materials for future information technology: status and prospects · Sci. China Inf. Sci. 2024
Emerging computing paradigms
neuromorphic hardware
0.212022
Neuromorphic sensory computing · Sci. China Inf. Sci. 2022

Methods — techniques the papers use, named apart from their topics

machine learning for material growth · 0.8
YearPublicationVenuePosition
2026 FOWLP-Based THz Quasi-Omnidirectional Antenna-in-Package for Chip-to-Chip Wireless Interconnect in AIoT
abstract
This paper presents a fan-out wafer-level package (FOWLP)-based terahertz (THz) quasi-omnidirectional antenna-in-package (AiP) for chip-to-chip (C2C) wireless interconnect in artificial intelligence of things (AIoT). The proposed design integrates key technological advancements, including packaging material characterization, the development and validation of vertical and horizontal interconnect structures and the quasi-omnidirectional antenna for THz applications. A novel copper-stacked substrate integrated waveguide (CS-SIW) multimode cavity, developed using FOWLP, enables broadband, high-precision dielectric characterization across the 150–270 GHz range, allowing accurate extraction of the dielectric constant and loss tangent. Additionally, a grounded coplanar waveguide (GCPW) with back-to-back transition validates the process performance in the THz band. The quasi-omnidirectional antenna, implemented on the redistribution layer (RDL), operates within the 215–230 GHz band, achieving a low profile of 0.0036λ0at 220 GHz and a peak gain of 2.13 dBi. Simulated and measured results demonstrate strong agreement, confirming the module's performance in terms of -10 dB impedance bandwidth and consistent radiation patterns. This work provides a promising solution for integrating compact, efficient THz AiP into future C2C wireless interconnect in AIoT.
Gang Zhuang, Shu Li Liu, Yang Chai
IEEE Internet Things J.4
2025 State Recognition Method of Power Equipment in Smart Grid Based on Machine Learning
abstract
In this paper, machine learning is used to solve the problem of power equipment state recognition, aiming to improve the accuracy of equipment operation state recognition. With the ever-expanding size of the power system, an increasing number of devices are becoming more intricate, posing significant challenges to the security of the electricity network. Consequently, enhancing equipment operational reliability is imperative to ensure the reliability of power system operations. This study focuses on the identification of the operating status of power equipment, which integrates intelligent optimization algorithms and machine learning techniques, utilizing an ameliorative FOA to solve the parameter setting problem of support vector machine (SVM). Subsequently, the new diagnosis model is utilized to distinguish the fault types of the equipment. Through simulation and measured data verification, it shows that the new power equipment state recognition model by using machine learning has high diagnostic accuracy. The method effectively enhances equipment status identification capabilities and equipment fault diagnosis proficiency.
Zhihui Kang, Yang Chai
Int. J. Pattern Recognit. Artif. Intell.3
2024 Two-dimensional materials for future information technology: status and prospects
abstract
Abstract Over the past 70 years, the semiconductor industry has undergone transformative changes, largely driven by the miniaturization of devices and the integration of innovative structures and materials. Two-dimensional (2D) materials like transition metal dichalcogenides (TMDs) and graphene are pivotal in overcoming the limitations of silicon-based technologies, offering innovative approaches in transistor design and functionality, enabling atomic-thin channel transistors and monolithic 3D integration. We review the important progress in the application of 2D materials in future information technology, focusing in particular on microelectronics and optoelectronics. We comprehensively summarize the key advancements across material production, characterization metrology, electronic devices, optoelectronic devices, and heterogeneous integration on silicon. A strategic roadmap and key challenges for the transition of 2D materials from basic research to industrial development are outlined. To facilitate such a transition, key technologies and tools dedicated to 2D materials must be developed to meet industrial standards, and the employment of AI in material growth, characterizations, and circuit design will be essential. It is time for academia to actively engage with industry to drive the next 10 years of 2D material research.
Hao Qiu 0001, Zhihao Yu, Tiange Zhao, Mingsheng Xu, Taotao Li, Wenzhong Bao, Yang Chai, Shula Chen, Hui-Ming Cheng, Daoxin Dai, Zengfeng Di, Zhuo Dong, Xidong Duan, Yuhan Feng, Jingshu Guo, Pengwen Guo, Yue Hao 0001, Jingyi Hu, Weida Hu, Zehua Hu, Ali Imran 0004, Ziqiang Kong, Bilu Liu, Chunsen Liu, Guanyu Liu, Kaihui Liu, Donglin Lu, Likuan Ma, Feng Miao, Zhenhua Ni, Anlian Pan, Haowen Shu, Quanyang Tao, Ziao Tian, Haomin Wang 0005, Yeliang Wang, Haidi Wu, Hongzhao Wu, Jiangbin Wu, Yanqing Wu, Longfei Xia, Baixu Xiang, Luwen Xing, Qihua Xiong, Jeffrey Xu, Yang Xu 0035, Yuekun Yang, Jincheng Zhang 0001, Tao Zhang 0090, Xinbo Zhang, Chunsong Zhao, Yuda Zhao, Ting Zheng, Peng Zhou 0021, Shaohua Kevin Zhou, Deren Yang
Sci. China Inf. Sci.9
2022 Neuromorphic sensory computing
Tianqing Wan, Sijie Ma, Fuyou Liao, Lingwei Fan, Yang Chai
Sci. China Inf. Sci.5
2011 Towards future VLSI interconnects using aligned carbon nanotubes
abstract
The copper interconnects cannot keep pace with the IC interconnect requirements as the feature size continues to scale down to nanoscale. Theoretical works predicted that carbon nanotube (CNT) is more superior than copper for future VLSI interconnects in terms of electrical conductivity, thermal management and reliability. Technology breakthroughs are required to bridge the gaps between the theoretical predictions and what is achievable with current CNT technology. In this paper, we shall describe our experimental efforts on the controlled growth of aligned CNTs; the integrations of CNT interconnects with IC technology; and the electrical characterization of the CNT interconnect. We also present the electro-migration test result of CNT-based interconnects to demonstrate the potential of CNT as robust VLSI interconnects. We hope our works provide useful data on the potential of CNT for VLSI interconnect applications.
Yang Chai, Min Zhang 0041, Philip C. H. Chan
VLSI-SoC1