This work presents a ring oscillator (RO)-based low-jitter injection-locked clock and data recovery (ILCDR) with a pattern-dependent pulse filtering (PDPF) technique. The conventional ILCDR has a drawback that data jitter is transferred to the recovered clock. To reduce jitter, the PDPF technique is employed to filter out the injection pulses occurring in data patterns that cause high data-dependent jitter (DDJ). Adopting the PDPF technique with an injection timing control loop, the ILCDR optimizes injection timing and maximizes timing margin. Fabricated in a 28-nm CMOS technology, the proposed ILCDR occupies an active area of 0.03 mm2and consumes 13.6 mW at 10 Gb/s. The measured jitter tolerance (JTOL) is 1 UIppat 35 MHz with a bit error rate (BER) of$10^{-12}$.

This paper presents a referenceless baud-rate clock and data recovery (CDR) circuit with an integrated pattern decoding technique for fast frequency acquisition. The proposed CDR achieves baud-rate frequency acquisition without edge sampling clock phase by utilizing an integrator circuit. The proposed integrated pattern decoding technique divides 6-bit sequential patterns into 5 pattern groups. The patterns of each pattern group are detected from the specific frequency offsets. By applying larger weights to the pattern groups including the patterns detected at the higher frequency offset, the proposed referenceless CDR achieves fast frequency acquisition. Fabricated in a 28-nm CMOS technology, the CDR prototype occupies 0.039 mm2and consumes 30.77 mW at 30 Gb/s. From various initial clock frequency, the proposed CDR achieves a capture range from 16 Gb/s to 30 Gb/s. Thanks to the fast frequency acquisition ability of the proposed integrated pattern decoding technique, the worst frequency acquisition time at the data rate of 30 Gb/s is$3.7~\mu $s. The CDR achieves a bit error rate (BER) of less than$10^{-12}$and an energy efficiency of 1.03 pJ/b.

This paper presents a single-ended three-level pulse amplitude modulation (PAM-3) transceiver employing crosstalk cancellation (XTC) techniques for next-generation memory interfaces. The proposed 3-ternery-to-4-ternery (3T4T) coding and feed-forward equalizer (FFE)-based XTC facilitate adopting PAM-3 signaling while maximizing channel density in the high-density memory interfaces. The proposed 3T4T coding reduces data-dependent jitter (DDJ) induced by inter-symbol interference (ISI) and mitigates the effect of crosstalk and maximum simultaneous noise (SSN) by half. The prototype transceiver is designed and fabricated in 28-nm CMOS process with a high-density on-chip channel which channel pitch is$1.0~\mu $m, obtaining an edge bandwidth density of 18 Tb/s/mm. The proposed PAM-3 transceiver achieves a crosstalk-induced jitter (CIJ) reduction of 0.846 unit interval (UI) with 90% CIJ reduction ratio at 18 Gb/s, and energy efficiencies of 1.103 pJ/bit and 0.764 pJ/bit for the transmitter and receiver, respectively. A bit error rate (BER) less than$10^{-12}$is verified with an eye margin of 0.40 UI.

This paper analyzes an effect of inter-wire skew on signal integrity in a multi-channel system and proposes circuit techniques to enhance signal integrity by using a spatially correlated coded signaling (SCCS). Through the in-depth analysis, the paper investigates a relation between skew and insertion loss (IL), and highlights an importance of wide-range inter-wire de-skewing (IWD). The proposed phase interpolator (PI)-based IWD technique adjusts the transition edges of receiver inputs to minimize skew caused by mismatch components, which increases timing jitter. The transceiver employs pseudo-differential signaling to verify the effect of the IWD in SCCS. The transmitter integrates a feed-forward equalizer (FFE) with a latch-based re-timer and a PI for each channel. Additionally, a 3-tap FFE at the transmitter and a continuous-time linear equalizer (CTLE) at the receiver are incorporated to compensate for channel ISI. Fabricated in 40-nm CMOS technology, the proposed 8-channel transceiver achieves an aggregate throughput of 112 Gb/s with a bit error rate (BER) below$10^{\mathbf {-12}}$. The transceiver occupies 0.382 mm2while achieving energy efficiencies of 0.77 pJ/bit/ch for the transmitter and 1.45 pJ/bit/ch for the receiver.