Tameesh Suri

dblp:68/1376 · DBLP profile ↗
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5ranked-venue papers
1as first author
0since 2021 · last 2015
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 1 first-authorSoftware engineering, systems software and programming languages · 2

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Performance modeling and evaluation · 51% Storage systems · 39% Processor architecture and microarchitecture · 10%
Network and information security
1 paper
Systems and software security · 100%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Storage systems
flash and SSD
0.212015
Performance Characterization of Hyperscale Applicationson on NVMe SSDs · SIGMETRICS 2015
Performance modeling and evaluation
workload characterization
0.212015
Performance Characterization of Hyperscale Applicationson on NVMe SSDs · SIGMETRICS 2015
Systems and software security › information flow tracking
dynamic information flow tracking
0.212014
SIFT: Low-Complexity Energy-Efficient Information Flow Tracking on SMT Processors · IEEE Trans. Computers 2014
Performance modeling and evaluation
storage performance evaluation
0.112015
Performance Characterization of Hyperscale Applicationson on NVMe SSDs · SIGMETRICS 2015
Processor architecture and microarchitecture › multithreading
simultaneous multithreading
0.112014
SIFT: Low-Complexity Energy-Efficient Information Flow Tracking on SMT Processors · IEEE Trans. Computers 2014

Methods — techniques the papers use, named apart from their topics

benchmarking · 0.2
YearPublicationVenuePosition
2015 Performance Characterization of Hyperscale Applicationson on NVMe SSDs
abstract
The storage subsystem has undergone tremendous innovation in order to keep up with the ever-increasing demand for throughput. NVMe based SSDs are the latest development in this domain, delivering unprecedented performance in terms of both latency and peak bandwidth. Given their superior performance, NVMe drives are expected to be particularly beneficial for I/O intensive applications in datacenter installations. In this paper we identify and analyze the different factors leading to the better performance of NVMe SSDs. Then, using databases as the prominent use-case, we show how these would translate into real-world benefits. We evaluate both a relational database (MySQL) and a NoSQL database (Cassandra) and demonstrate significant performance gains over best-in-class enterprise SATA SSDs: from 3.5x for TPC-C and up to 8.5x for Cassandra.
Qiumin Xu, Huzefa Siyamwala, Mrinmoy Ghosh, Manu Awasthi, Tameesh Suri, Zvika Guz, Anahita Shayesteh, Vijay Balakrishnan
SIGMETRICS5
2015 Performance analysis of NVMe SSDs and their implication on real world databases
abstract
The storage subsystem has undergone tremendous innovation in order to keep up with the ever-increasing demand for throughput. Non Volatile Memory Express (NVMe) based solid state devices are the latest development in this domain, delivering unprecedented performance in terms of latency and peak bandwidth. NVMe drives are expected to be particularly beneficial for I/O intensive applications, with databases being one of the prominent use-cases.
Qiumin Xu, Huzefa Siyamwala, Mrinmoy Ghosh, Tameesh Suri, Manu Awasthi, Zvika Guz, Anahita Shayesteh, Vijay Balakrishnan
SYSTOR4
2015 System-Level Characterization of Datacenter Applications
abstract
In recent years, a number of benchmark suites have been created for the ``Big Data'' domain, and a number of such applications fit the client-server paradigm. A large volume of recent literature in characterizing ``Big Data'' applications have largely focused on two extremes of the characterization spectrum. On one hand, multiple studies have focused on client-side performance. These involve fine-tuning server-side parameters for an application to get the best client-side performance. On the other extreme, characterization focuses on picking one set of client-side parameters and then reporting the server microarchitectural statistics under those assumptions. While the two ends of the spectrum present interesting results, this paper argues that they are not enough, and in some cases, undesirable, to drive system-wide architectural decisions in datacenter design.
Manu Awasthi, Tameesh Suri, Zvika Guz, Anahita Shayesteh, Mrinmoy Ghosh, Vijay Balakrishnan
ICPE2
2014 SIFT: Low-Complexity Energy-Efficient Information Flow Tracking on SMT Processors
abstract
Dynamic information flow tracking (DIFT) is a powerful technique that can protect unmodified binaries from a broad range of vulnerabilities including buffer overflow and format string attacks. Software DIFT implementations suffer from very high performance overheads, while comprehensive hardware implementations add substantial complexity to the microarchitecture, making it unlikely for chip manufacturers to adopt them. In this paper, we propose SIFT (SMT-based DIFT), where a separate thread performing taint propagation and policy checking is executed in a spare context of an SMT processor. The instructions for the checking thread are generated in hardware using self-contained off-the-critical path logic at the commit stage of the pipeline. We investigate several performance optimizations to the base design including: 1) Prefetching of the taint data from shadow memory when the corresponding data is accessed by the primary thread; 2) Optimizing the generation of the taint code to remove unneeded security instructions; and 3) The use of aggregated instructions for collapsing the frequently used groups of security instructions into a single new instruction. Together, these optimizations reduce the performance penalty of SIFT to under 20 percent on SPEC CPU 2006 benchmarks-much lower than the overhead of previously proposed software-based DIFT schemes. We also analyze the energy overhead of SIFT and show it to be very high - 113 percent for SPEC 2006 benchmarks. We then propose several techniques that reduce this overhead to only 23 percent, making SIFT design practical from the energy standpoint. To demonstrate the feasibility of SIFT, we design and synthesize a core with SIFT logic and show that the area overhead of SIFT is only 4.5 percent and that instruction generation can be performed in one additional cycle at commit time.
Meltem Ozsoy, Dmitry V. Ponomarev, Nael B. Abu-Ghazaleh, Tameesh Suri
IEEE Trans. Computers4
2008 Scalable Multi-cores with Improved Per-core Performance Using Off-the-critical Path Reconfigurable Hardware
Tameesh Suri, Aneesh Aggarwal
HiPC1