Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page
Demo Data from EDBT 2026 / reviewers in the wild / expert

Anucha Pitaksanonkul

dblp:68/176 · DBLP profile ↗
← Back
3ranked-venue papers
3as first author
0since 2021 · last 1989
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 3 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 80% Hardware reliability and fault tolerance · 20%
Theoretical computer science
1 paper
Computational geometry · 50% Algorithms and data structures · 50%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
physical design		 0.021989
Comparisons of quad trees and 4-D trees: new results [VLSI layout] · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1989
DTR: A Defect-Tolerant Routing Algorithm · DAC 1989
Electronic design automation › physical design › routing
channel routing		 0.011989
DTR: A Defect-Tolerant Routing Algorithm · DAC 1989
Hardware reliability and fault tolerance
defect tolerance		 0.011989
DTR: A Defect-Tolerant Routing Algorithm · DAC 1989
Electronic design automation › physical design
VLSI layout		 0.011989
Comparisons of quad trees and 4-D trees: new results [VLSI layout] · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1989
Computational geometry
spatial data structures		 0.011989
Comparisons of quad trees and 4-D trees: new results [VLSI layout] · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1989
Algorithms and data structures
tree data structures		 0.011989
Comparisons of quad trees and 4-D trees: new results [VLSI layout] · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1989

Methods — techniques the papers use, named apart from their topics

region query · 0.0quadtree · 0.04-d tree · 0.0channel routing algorithm · 0.0
YearPublicationVenuePosition
1989 DTR: A Defect-Tolerant Routing Algorithm
abstract
A new channel routing algorithm called DTR (Defect-Tolerant Routing) is investigated. This algorithm minimizes the total area and simultaneously maximizes the performance by reducing the critical area which can potentially be the source of logical faults caused by the bridging effects of spot defects. Experimental results show DTR produces less critical area than Yoshimura&Kuh's algorithm [1].
Anucha Pitaksanonkul, Suchai Thanawastien, Chidchanok Lursinsap, J. A. Gandhi
 DAC1
1989 Bisection trees and half-quad trees: Memory and time efficient data structures for VLSI layout editors
Anucha Pitaksanonkul, Suchai Thanawastien, Chidchanok Lursinsap
 Integr.1
1989 Comparisons of quad trees and 4-D trees: new results [VLSI layout]
abstract
A comparison is made between two tree data structures that support region queries for VLSI layout systems. In a previous study, J.B. Rosenberg (ibid., vol.CAD-4, no.1, p.53-67, 1985) demonstrated that four-dimensional trees have a faster speed but use more memory space than quad trees with bisector lists. In this study the authors show that quad trees without bisector lists, for some small threshold values, have a better speed and require less storage than four-dimensional trees.>
Anucha Pitaksanonkul, Suchai Thanawastien, Chidchanok Lursinsap
 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1