The compaction of IC layouts subjected to conditional spacing rules in multiple-level metal technology is addressed. The constraints imposed by conditional rules make the automatic compaction of layout much more difficult than when the usual minimum separation rules are applied. To solve the problem, each conditional spacing rule is formulated with a set of arcs in the constraint graph representation. It is proven that finding the optimal solution under one bridge rule is NP-complete. A graph-theory method of compaction which, by reducing the problem size, can efficiently obtain an optimal solution is proposed.>

A popular algorithm to compact VLSI symbolic layout is to use a graph algorithm similar to finding the "longest path" in a network. The algorithm assumes that the spacing constraints on the mask elements are of the lower bound type. However, to enable the user to have close control over the compaction result, a desired symbolic layout system should allow the user to add either the equality or the upper bound constraints on selected pairs of mask elements as well. This paper proposes an algorithm which uses a graph-theoretic approach to solve efficiently the compaction problem with mixed constraints.