Reducing heat dissipation is critical for modern multi-core systems to meet increasing computational performance requirements. In this paper, we investigate the impact of idle-time distribution on the peak temperature of Multi-processor System-on-Chip (MPSoCs) for the constrained-deadline non-preemptive task scheduling problem that is common in safety-critical systems. It is assumed that the transient thermal behavior of the platform cannot be neglected and must be modeled and accounted for by the optimization algorithms. In this context, we derive a dual-node thermal model that can be well applied to a dual-cluster i.MX8 QuadMax from NXP. Based on this model, we implement two offline optimization-based strategies, including an iterative per-core approach based on the principles presented in the related literature and a novel holistic approach. The results show that the per-core approach and the holistic approach reduce the peak temperature by 7.1% and 14% on average compared to the traditional non-thermal approach. We perform the experiments on the i.MX8 QuadMax platform to validate the applicability of the results and observe a good match between the model-based simulations and the actual physical platform measurements.

With the advent of modern multi-core architectures, the problem of scheduling complex real-time applications has become one of the major challenges in developing safety-critical systems. In this context, existing solutions typically rely on greedy, hand-crafted heuristics and/or pessimistic tests that fail to meet the expected high performance and timing guarantees. This paper advocates an efficient learning-based scheduling framework that automatically generates an adaptive policy for a given workload and platform, thereby mitigating these limitations.

The IEEE Time-Sensitive Networking (TSN) Task Group specifies a set of standards that enables real-time communication with predictable and bounded delays over the Ethernet. Specifically, TSN introduces a new set of so-called shapers, which regulate traffic arrival and transmission in the networks. Prominent among those are the IEEE 802.1 Qbv Time Aware Shaper (TAS) and IEEE 802.1Qav Credit-Based Shaper (CBS). Another traffic control mechanism is the IEEE 802.1Qbu Frame Preemption. Most works in the literature have focused on the quantitative performance comparison between these mechanisms. However, the discussion on how they compare in terms of implementation cost has received less attention. In this paper, we provide a comprehensive comparison of the implementation cost of the aforementioned TSN traffic control mechanisms. This comparison can help system designers in choosing which of the mechanism(s) to deploy for their applications.

To overcome the limitation of strictly non-preemptive frame transmission in Ethernet networks, the IEEE 802.1Qbu standard was introduced. This standard specifies a one-level frame preemption paradigm wherein, depending on their priority levels, frames are grouped into two categories: namely, the “express frames” and the “preemptable frames”. These two categories are given with the interpretation that (1) only express frames can preempt preemptable frames; and (2) two frames belonging to the same category cannot preempt each other. While this approach partially solves the problem, some preemptable frames can still suffer long blocking periods, irrespective of their individual priority levels. Indeed, there are frames that do not fall into the express frames category, but nevertheless have firm timing requirements that can only be met if they can benefit from preempting lower priority frames. To ameliorate the condition of such frames, we propose a multi-level preemption paradigm. Specifically, we expose the limitations of the one-level preemption approach experimentally; and we present the feasibility and implementation requirements of the multi-level preemption scheme in details.

On-chip power dissipation is recognized as one of the primary limiters, if not a show stopper, of performance for high-end safety-critical uniform multi-core processors. This paper proposes an efficient and simple thermal model for such a platform to be coupled with the large variety of schedulers designed to control the processor activity and the triggering of the cooling mechanism with as little impact on performance as possible.

The rising adoption of wireless technologies in the In- dustrial Internet of Things has stressed the need for traffic schedulability validation at system design-time to support safety and time critical streams (e.g., process control and emergency response). In this context, the demand-based schedulability tests have recently been proposed in the literature. This work revisits two well-established techniques borrowed from the multi-processor scheduling theory, namely the demand-bound-function (DBF) and the forced-forward-demand-bound-function (FFDBF), and evaluates their performances when adapted to the field of wireless sensor-actuator networks. Simulation experiments when varying network configurations confirm the equal or better accuracy of FFDBF over DBF to estimate both network demand and schedulability. In future work, we aim at building upon these promising results in order to design novel admission control and adaptation strategies that improve network schedulability under varying workload conditions.

Technology advances in microprocessor design have resulted in high device density and performance during the last decades. More components are fabricated on the chip die and millions, if not billions, of instructions can now be executed within microseconds. A consequence of this advancement is heat dissipation by the microprocessors. In this context, elevated on-chip temperature issues have become an important subject for the design of future generations of microprocessors, especially in avionics and automotive industries. In this paper, we address the scheduling problem of non-preemptive periodic tasks on a single processor platform under thermal-aware design. We assume that the tasks are scheduled by following any Fixed-Task-Priority (FTP) scheduler (e.g., Rate Monotonic (RM) or Deadline Monotonic (DM)) and we propose a unique framework wherein we capture both the temporal and thermal behavior of the system. Then, we present two new thermal-aware scheduling strategies, referred to as NP-HBC and NP-CBH, to keep the system temperature within specified parameters and we derive their respective schedulability analysis. Finally, we evaluate the performance of the proposed theoretical results through intensive simulations.

There is an increasing eagerness to deploy and execute parallel applications on many-core infrastructures, preserving the time-predictability of the execution as required by real-time practices to upper-bound the response time of the embedded application. In this context, the paper discusses the application of the currently-available WCET analysis techniques and tools on such platforms and with highly parallel activities. After discussing the pros and cons of all different methodologies for WCET analysis, we introduce a new approach that is developed within the P-SOCRATES project.

This paper explores the behavior of parallel fork-join tasks on multicore platforms by resorting to a semi-partitioned scheduling model. This model offers a promising framework to embedded systems which are subject to stringent timing constraints as it provides these systems with very interesting properties. The proposed approach consists of two stages -- an offline stage and an online stage. During the offline stage, a multi-frame task model is adopted to perform the fork-join task-to-core mapping so as to improve the schedulability and the performance of the system, and during the online stage, work-stealing is exploited among cores to improve the system responsiveness as well as to balance the execution workload. The objective of this work is twofold: (1) to provide an alternative technique that takes advantage of the semi-partitioned scheduling properties by offering the possibility to accommodate fork-join tasks that cannot be scheduled in any pure partitioned environment, and (2) to reduce the migration overhead which has shown to be a traditional major source of non-determinism in global approaches. The simulation results show an improvement of the proposed approach over the state-of-the-art of up to 15% of the average response-time per task set.

A steady increase in the number of cores within many-core platforms causes increasing contentions for the interconnect medium and leads to non-negligible latencies of intercore communication. In order to study the worst-case execution times of applications, it is no longer sufficient to only take into account schedulability requirements, but the communication delays also have to be considered. In this paper we focus on the worst-case communication delays of applications, assuming a Limited Migrative Model (LMM). LMM is an approach based on the multi-kernel paradigm - a promising step towards scalable and predictable many-cores. The contribution of this paper is threefold. First, we extend LMM by allowing inter-application communication, and adapt the existing worst-case communication delay analysis, to make it applicable to the enhanced model. Then, we propose a novel analysis. Finally, we compare these two methods. The experiments show that the new approach renders tighter upper-bound estimates in more than 90% of the cases, while demonstrating a comparable runtime performance.

The ratio between the number of cores and memory subsystems (i.e. banks and controllers) in many-core platforms is constantly increasing, leading to non-negligible latencies of memory operations. Thus, in order to study the worst-case execution time of an application, it is no longer sufficient to only take into account its computational requirements, but also have to be considered latencies related to its memory operations. In this paper we study a limited migrative model applied upon many-core platforms. This approach is based on a multi-kernel paradigm [3] - a promising step towards scalable and predictable many-cores, which are essential prerequisites for the integration of such systems into the real-time embedded domain. Under that assumption, we present two analytical methods to obtain the worst-case memory traffic delays of individual applications. Through experiments we test the applicability of the proposed approaches to different scenarios, and draw practical conclusions concerning routing mechanisms and a distribution of memory operations across memory controllers.

Modeling and analysis of timing information are essential to the design of real-time systems. In this domain, research related to probabilistic analysis is motivated by the desire to refine results obtained using worst-case analysis for systems in which the worst-case scenario is not the only relevant one, such as soft real-time systems. This paper presents an overview of the existing solutions for probabilistic timing analysis, focusing on challenges they have to face. We discuss in particular two new trends toward Probabilistic Real-Time Calculus and Typical-Case Analysis which rise to some of these challenges.

A challenging research issue of analyzing a real-time system is to model the tasks composing the system and the resource provided to the system. In this paper, we propose a probabilistic component-based model which abstracts in the interfaces both the functional and non-functional requirements of such systems. This approach allows designers to unify in the same framework probabilistic scheduling techniques and compositional guarantees that go from soft to hard real-time. We provide sufficient schedulability tests for task systems using such framework when the scheduler is either preemptive Fixed-Priority or Earliest Deadline First.

In this paper, we address the scheduling problem of multi-mode real-time systems upon uniform multiprocessor platforms. We propose two transition protocols, specified together with their schedulability test, and provide the reader with two distinct upper bounds for the length of the transient phases during mode transitions, respectively for the cases where jobs priorities are known and unknown beforehand.

In this paper we study hard real-time systems composed of independent periodic preemptive tasks where we assume that tasks are scheduled by using Liu & Layland's pioneering model following the Rate Monotonic Analysis (RMA). For such systems, the designer must guarantee that all the deadlines of all the tasks are met, otherwise dramatic consequences occur. Certainly, guaranteeing deadlines is not always achievable because the preemption is approximated when using this analysis, and this approximation may lead to a wrong real-time execution whereas the schedulability analysis concluded that the system was schedulable. To cope with this problem the designer usually allows margins which are difficult to assess, and thus in any case lead to a waste of resources. This paper makes multiple contributions. First, we show that, when considering the cost of the preemption during the analysis, the critical instant does not occur upon simultaneous release of all tasks. Second, we provide a technique which counts the exact number of preemptions of each instance for all the tasks of a given system. Finally, we present an RMA extension which takes into account the exact cost due to preemption in the schedulability analysis rather than an approximation, thus yielding a new and stronger schedulability condition which eliminates the waste of resources since margins are not necessary.

Classical off-line approaches based on preemption such as RM (rate monotonic), DM (deadline monotonic), EDF (earliest deadline first), LLF (least laxity first), etc, give schedulability conditions but most of the time assuming on the one hand that all the tasks are independent, and on the other hand, that the first instances of all tasks are released at the same time. We are interested in hard real-time systems subject to precedence and strict periodicity constraints, i.e. such that for all instances of each task, the release time and start time are equal. For such systems, it is mandatory to satisfy these constraints. In this paper we give non-schedulability conditions in order to restrict the study field of all systems of tasks to only potentially schedulable systems.