We present a subjective review of custom cellgeneration methods in the context of future advances instate-of-the-art digital circuit synthesis. In particular, wedescribe three opportunities for coupling circuitoptimization operations with the library developmentprocess. These operations include electrical optimization,technology mapping, and cell level place and route.

This paper describes a one-dimensional compactor which simultaneously compacts the contents of all cells of a layout hierarchy without changing the hierarchy. The compactor performs both compaction and wire length minimization hierarchically using the power of the Simplex method for linear programs. Compaction of arrays, compaction of overlapping cells, and symmetry preserving compaction are also handled, since these are special cases of layout hierarchies. Using dedicated Simplex algorithms for compaction and wire length minimization, a globally optimum result is produced quickly and efficiently without the use of protection frames or domains and terminals. The compactor corrects design rule violations, preserves wire widths, and maintains terminal connections automatically. It does not yet introduce jogs in wires automatically. Results are provided for a few CMOS modules, including a ROM and an SRAM core.

A VLSI layout design system named Tailor is described. Tailor operates on hierarchical layouts containing 45 degrees multiple angles. It consists of a well-integrated set of tools, including a window-driven editor, an incremental design rule checker, a circuit extractor, a one-dimensional compactor, a channel-based global router, and a transistor size optimizer. All tools use the same user interface and operate directly on Tailor's trapezoidal corner stitched database. Tailor's database structure is well suited for all of the tools because all important database operations, such as point searching, neighbor searching, area searching, and shadow searching, function very efficiently. All the tools in Tailor, except transistor optimization and routing, work directly on the layout hierarchy, which provides even greater efficiency.>

This paper describes a combination transistor sizing/layout compaction tool used to synthesize high performance CMOS circuits. This optimization tool is part of a large integrated layout system, called Tailor. Given any CMOS circuit layout, Tailor's transistor size optimizer will simultaneously adjust transistor sizes and compact the layout so that the minimum required area (cell pitch) for a specified upper bound on circuit delay is achieved. All delay paths are considered by modeling circuit delay with a logic independent delay graph. Tailor's optimizer globally optimizes circuit area (in one dimension) and delay by use of compaction and nonlinear programming algorithms. The optimizer does not yet optimize in two dimensions simultaneously or optimize hierarchical circuits. Results for a few optimized CMOS circuits are presented.