The number fluctuation theory based on the McWhorter's charge-trapping model and the bulk mobility fluctuation theory based on Hooge's hypothesis are the two major existing theories to explain the origins of the flicker noise, which is the dominant low-frequency noise source in silicon metal-oxide-semiconductor field-effect transistors (MOSFETs). We have done the flicker noise measurements and SPICE simulations for both long-channel (5 /spl mu/m) and short-channel (1.2 /spl mu/m and 0.6 /spl mu/m) p-type channel metal-oxide-semiconductor (PMOS) transistors. HSPICE [device model: level 3, level 46 (BSIM 3v2) and level 47 (BSIM 3v3); noise model: NLEV=0 and NLEV=2 and 3] and PSPICE [device model: level 3, level 6 (BSIM 3v2) and level 7 (BSIM 3v3); noise model: NLEV=0 and NLEV=2 and 3] were used for the simulations. Our measurement results suggest that in the saturation region, for long-channel PMOS transistors, the flicker noise is due to the bulk effect and it follows the mobility fluctuation theory, while for short-channel ones, it is due to the surface state effect and the number fluctuation theory applies. Our simulation results showed that for both HSPICE and PSPICE, level 3 and NLEV=0 are the appropriate models for the simulations of long-channel PMOS transistor flicker noise; HSPICE with level 47 or 49 and NLEV=2 and 3 and PSPICE with level 6 and NLEV=2 and 3 are applied for the short-channel PMOS devices. The simulation results are consistent with the measurements.

The two main sources of low-frequency flicker noise are mobility fluctuations and number fluctuations. Our experiments on NMOS noise measurements were done from subthreshold to saturation region of operation for both long-channel (5 /spl mu/m) and short-channel (as small as 0.6 /spl mu/m) NMOS transistors. The results suggest that for both types that in the saturation region, the flicker noise is due to the surface state effect and the noise equations, NLEV=2 and 3, in SPICE, HSPICE, and PSPICE are most appropriate. For short-channel devices, due to the effects of velocity saturation and the resulting nonlinear transconductance (g/sub m/) variation with gate bias voltage, the input-referred voltage noise increases as the gate-source voltage increases instead of staying constant as it does for long-channel devices. In the subthreshold region, the input-referred voltage noise decreases drastically as the gate-source voltage increases for both long-channel and short-channel NMOS devices. Simulations have been done using PSPICE and HSPICE, with noise level (NLEV)=3 and device model level 3 and BSIM 3.2 and 3.3. The results from PSPICE version 8.0 level 7 (BSIM 3.3) and SPICE level 3 compare favorably with the measured noise phenomena for the short-channel and long-channel NMOS devices, respectively.

This report describes a successful simulation using HSPICE and comparison with published data of the phase noise on a 2-GHz CMOS inductance-capacitance (LC) oscillator caused by low-frequency flicker noise (1/f noise). The flicker noise, which is determined by measurements on NMOSFETs, is simulated as a sum of sine waves with random phase by using MATLAB, and is finally introduced into the LC oscillator circuit as an HSPICE piecewise linear waveform. The output of LC oscillator in HSPICE is written as a series of points equally spaced in time and then the spectrum is computed by fast Fourier transform (FFT). The simulation results show the phase noise of the voltage-controlled oscillator with different noise coefficient (KF) values in the SPICE models, and demonstrate that the phase noise caused by low-frequency flicker noise has a 1/f/sup 3/ dependence on the offset frequency. The simulated sideband power spectral density corresponds to the measured values reported in the literature.