The report, Curriculum Guidelines for Undergraduate Degree Programs in Computer Engineering (CE2016), developed by the Association for Computing Machinery and the IEEE Computer Society, was released in December of 2016. This is one volume of a series of reports covering curricula for a variety of computing fields; it is a significant update of the previous version, CE2004. This paper discusses significant aspects of CE2016, with a focus on how the report might be used in reviewing, updating, and creating computer engineering programs.

Joint ACM/IEEE Computer Society undergraduate computer engineering curriculum guidelines are slated for release in 2016. These update the 2004 guidelines commonly known as CE2004. The presenters are part of the task group leading the revisions and will give an overview of the latest draft. Participants will engage in discussions on potential improvements to the guidelines to ensure that they are useful to programs as they work to ensure their curricula reflect the state-of-the-art in computer engineering education and practice and are relevant for the coming decade.

The audience will discuss the current state of the effort to update the 2004 document titled "Curriculum Guidelines for Undergraduate Degree Programs in Computer Engineering," also known as CE2004. The presenters represent the ACM and the IEEE Computer Society (IEEE-CS), which are leading the effort. They will engage participants on ways of improving the body of knowledge so that the document reflects the state-of-the-art of computer engineering education and practice that is relevant for the coming decade.

The integrated yield-reliability model for integrated circuits allows one to estimate the yield, following both wafer probe and burn-in testing. The model is based on the long observed clustering of defects and the experimentally verified relation between defects causing wafer probe failures, and defects causing infant mortality failures. The 2-parameter negative binomial distribution is used to describe the distribution of defects over a semiconductor wafer. The clustering parameter /spl alpha/, while known to play a key role in accurately determining wafer probe yields, is shown, for the first time, to play a similar role in determining burn-in fall-out. Numerical results indicate that the number of infant mortality failures predicted by the clustering model can differ appreciably from calculations that ignore clustering. This is particularly apparent when wafer probe yields are low, and clustering is high.

Integrated circuits can exhibit significant early life or infant mortality failures. Methods to estimate and/or reduce the number of such failures are therefore of great interest to industry. Applications employing multi-chip modules (MCMs), where several die must be independently reliable, are particularly vulnerable to early life failures. Maximizing the reliability of each die is therefore of significant importance. This paper presents an integrated yield-reliability model that allows one to estimate the number of burn-in failures for repairable memory chips, a common component in many MCMs. Since defects in integrated circuits tend to cluster, memory chips that have been repaired have a greater chance of containing a latent defect than chips with no repairs. The result is a higher incidence of infant mortality failure among memory chips that have been repaired.

Defects have long been known to cluster on semiconductor wafers. Recent research has shown that this fact may be exploited to produce die of high reliability, (i.e. decreased infant mortality), by sorting die into bins based on how many of their neighbors test faulty. Die that test good at wafer probe, yet come from neighborhoods with many faulty die, have a higher incidence of infant mortality failure than die from neighborhoods with few faulty die. Analysis of burn-in results from the SEMATECH test methods experiment suggests that such a binning approach has the potential to isolate a high quality bin that displays very few burn-in failures. This paper presents the first analytical model that quantifies the reliability improvement one might expect when binning die based on local region yield.

A message-passing computer architecture called the modified mesh-connected parallel computer (MMCPC) is proposed and studied. The MMCPC is designed to be general-purpose parallel architecture suitable for wafer-scale integration. Generalized stochastic Petri nets (GSPNs) are used to model the behavior of the MMCPC. The GSPN performance modeling results show a need for a new processing element (PE). A PE architecture, able to handle data processing and message passing concurrently, is proposed, and the silicon overhead is estimated in comparison with transputerlike PEs. Based on the proposed PE, optimum sizes of the MMCPC for different program structures are derived. A two-dimensional fast Fourier transform problem is used as an example to demonstrate that the MMCPC is a cost-effective performance-enhancement architecture to a real problem.>

A failure-dependent bandwidth model for shuffle-exchange (S/E) and augmented shuffle-exchange (S/E+) interconnection networks is presented. The models are based on probabilities of either data or address model failures for the individual binary switches that comprise the network and give the expected bandwidth as a function of the probability of failures in these switches. A model consistent with those previously published for a zero probability of failure is first developed for the S/E network. It is extended to the S/E+ network by developing a special model for the input stage of the S/E+ network and then proving that, to within a close approximation, the conditions necessary for the S/E model hold at the outputs of first stage of the S/E+. The primary uses of the bandwidth models presented are as a network design parameter and as a measure to evaluate the cost effectiveness of proposed, switch-level, reliability enhancement.>

The use of shuffle/exchange (S/E) interconnection networks in multiprocessor systems has been proposed for several applications. In order to evaluate the potential performance and reliability of such systems, the effects of conflicts involving switch and memory contention should be determined. This paper presents a discrete Markov chain model to study the effects of such contention for S/E networks used in random access application environments. This model is used to derive memory bandwidth (MBW) of the system, with analytic expressions presented for 4 X 4 and 8 X 8 S/E networks. Two cases are considered. First, the model is applied to systems in which all processors issue their access requests synchronously, then this model is used to construct a traffic model which allows the generation of access requests at arbitrary times. The results of the analysis are compared with simulation results and the analytical results derived by Bhandarkar for the full Crossbar network. Besides the MBW, other interference-related parameters such as blocking probability, traffic, loading, and blocking delay are discussed. In particular, the loading effect of a 16 X 16 S/E network obtained from the model is compared with the results of the simulation from Wirsching's CONET model.