Demo Data from EDBT 2026 / reviewers in the wild / expert
Junji Sakai
dblp:68/3810
· DBLP profile ↗
7ranked-venue papers
0as first author
0since 2021 · last 2011
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 6Computer networks · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Cloud and datacenter computing · 100% | |
| Network and information security
1 paper |
Systems and software security · 100% |
Topics — the 1 heaviest of 2, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Cloud and datacenter computing › virtualization › resource virtualization
processor virtualization |
0.1 | 1 | 2006 | VIRTUS: a new processor virtualization architecture for security-oriented next-generation mobile terminals · DAC 2006 |
Methods — techniques the papers use, named apart from their topics
virtualization-assist logic · 0.1virtual machine monitor asymmetrization · 0.1dynamic inter-domain communication · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2011 | Greening of Many-Core Processors in Network-Optimized ComputingabstractThis paper presents adaptive performance control for many-core processors in response to network traffic in order to reduce power dissipation. It presents two new techniques: smart core-number control, which averages out both performance and power dissipation by disabling inactive CPU cores, and smart core-performance control, which quickly adjusts both performance and power dissipation in each active CPU core by using a dynamic thermal controller. Evaluation results for a 1.8GHz 16-core/64-thread IBM PowerEN processor show that smart core-number control reduces power dissipation by 46% under low network traffic conditions and smart core-performance control reduces power dissipation by 21% even when large network traffic fluctuates by 80% for a short time. Hiroaki Inoue, Kazuhisa Ishizaka, Junji Sakai |
GLOBECOM | 3 |
| 2010 | A robust seamless communication architecture for next-generation mobile terminals on multi-CPU SoCsabstractWe propose a robust seamless communication architecture that enables legacy mobile terminal software designed for single-CPU processors to be run on multi-CPU processors without any software modifications. This architecture features two new technologies: proxy processes, which help achieve the design of its user-level system-call hooking and a robust design method, which reduces bandwidth variation by systematic parameter optimization. Our evaluations confirmed that this architecture achieves fundamental features with satisfactory performance, that we have succeeded in getting actual mobile terminal software to run on three CPUs without modifying the software, and that the robust design method reduces bandwidth variation by 21%. Hiroaki Inoue, Junji Sakai, Masato Edahiro |
ACM Trans. Embed. Comput. Syst. | 2 |
| 2009 | Dynamic security domain scaling on embedded symmetric multiprocessorsabstractWe propose a method for dynamic security-domain scaling on SMPs that offers both highly scalable performance and high security for future high-end embedded systems. Its most important feature is its highly efficient use of processor resources, accomplished by dynamically changing the number of processors within a security-domain (i.e., dynamically yielding processors to other security-domains) in response to application load requirements. Two new technologies make this scaling possible without any virtualization software: (1) self-transition management and (2) unified virtual address mapping. Evaluations show that this domain control provides highly scalable performance and incurs almost no performance overhead in security-domains. The increase in OSs in binary code size is less than 1.5%, and the time required for individual state transitions is on the order of a single millisecond. This scaling is the first in the world to make possible the dynamic changing of the number of processors within a security-domain on an ARM SMP. Hiroaki Inoue, Tsuyoshi Abe, Kazuhisa Ishizaka, Junji Sakai, Masato Edahiro |
ACM Trans. Design Autom. Electr. Syst. | 4 |
| 2008 | FIDES: An advanced chip multiprocessor platform for secure next generation mobile terminalsabstractWe propose a secure platform on a chip multiprocessor, FIDES, in order to enable next generation mobile terminals to execute downloaded native applications for Linux. Its most important feature is the higher security based on multigrained separation mechanisms. Four new technologies support the FIDES platform: bus filter logic, XIP kernels, policy separation, and dynamic access control. With these technologies, the FIDES platform can tolerate both application-level and kernel-level bugs on an actual download subsystem. Thus, the best-suited platform to secure next generation mobile terminals is FIDES. Hiroaki Inoue, Junji Sakai, Sunao Torii, Masato Edahiro |
ACM Trans. Embed. Comput. Syst. | 2 |
| 2008 | Processor virtualization for secure mobile terminalsabstractWe propose a processor virtualization architecture, VIRTUS, to provide a dedicated domain for preinstalled applications and virtualized domains for downloaded native applications. With it, security-oriented next-generation mobile terminals can provide any number of domains for native applications. VIRTUS features three new technologies, namely, VMM asymmetrization, dynamic interdomain communication (IDC), and virtualization-assist logic, and it is first in the world to virtualize an ARM-based multiprocessor. Evaluations have shown that VMM asymmetrization results in significantly less performance degradation and LOC increase than do other VMMs. Further, dynamic IDC overhead is low enough, and virtualization-assist logic can be implemented in a sufficiently small area. Hiroaki Inoue, Junji Sakai, Masato Edahiro |
ACM Trans. Design Autom. Electr. Syst. | 2 |
| 2007 | Towards scalable and secure execution platform for embedded systemsabstractReliability of embedded systems can be enhanced by multicore and partitioning approaches. Physical partitioning based on AMP multicore achieves runtime stability of multiple applications in a system and prevents the whole system shutdown as well even when a malicious code creeps in. Combined with logical partitioning by processor visualization and SMP technologies, the multicore architecture could realize more flexible and more scalable platform for future embedded systems. Hiroaki Inoue, Masato Edahiro, Junji Sakai |
ASP-DAC | 3 |
| 2006 | VIRTUS: a new processor virtualization architecture for security-oriented next-generation mobile terminalsabstractWe propose a new processor virtualization architecture, VIRTUS, to provide a dedicated domain for pre-installed applications and virtualized domains for downloaded native applications. With it, security-oriented next-generation mobile terminals can provide any number of domains for native applications. VIRTUS features three new technologies: VMM asymmetrization, dynamic inter-domain communication and virtualization-assist logic, and it is first in the world to virtualize an ARM-based multiprocessor. Hiroaki Inoue, Akihisa Ikeno, Masaki Kondo, Junji Sakai, Masato Edahiro |
DAC | 4 |