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Romain Cledat

dblp:68/3973 · DBLP profile ↗
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8ranked-venue papers
2as first author
0since 2021 · last 2017
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 5 · 1 first-authorSoftware engineering, systems software and programming languages · 2 · 1 first-authorApplied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
4 papers
Memory systems · 47% Parallel and multicore computing · 19% Performance modeling and evaluation · 8%

Topics — the 14 heaviest of 16, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems
data locality
0.312017
Trends in Data Locality Abstractions for HPC Systems · IEEE Trans. Parallel Distributed Syst. 2017
Memory systems
data movement
0.312017
Trends in Data Locality Abstractions for HPC Systems · IEEE Trans. Parallel Distributed Syst. 2017
Memory systems › memory hierarchy
memory hierarchy management
0.312017
Trends in Data Locality Abstractions for HPC Systems · IEEE Trans. Parallel Distributed Syst. 2017
Parallel and multicore computing
parallel programming models
0.222017
Efficiently speeding up sequential computation through the n-way programming model · OOPSLA 2011
Trends in Data Locality Abstractions for HPC Systems · IEEE Trans. Parallel Distributed Syst. 2017
Processor architecture and microarchitecture
many-core architecture
0.212013
Runnemede: An architecture for Ubiquitous High-Performance Computing · HPCA 2013
Energy-efficient computing › voltage scaling
near-threshold voltage operation
0.212013
Runnemede: An architecture for Ubiquitous High-Performance Computing · HPCA 2013
Memory systems
on-chip memory
0.212013
Runnemede: An architecture for Ubiquitous High-Performance Computing · HPCA 2013
Parallel and multicore computing
speculative parallelization
0.112011
Efficiently speeding up sequential computation through the n-way programming model · OOPSLA 2011
Parallel and multicore computing
parallel programming runtimes
0.112017
Trends in Data Locality Abstractions for HPC Systems · IEEE Trans. Parallel Distributed Syst. 2017
Electronic design automation
design optimization
0.112007
A profile-driven statistical analysis framework for the design optimization of soft real-time applications · ESEC/SIGSOFT FSE 2007
Performance modeling and evaluation
profiling
0.112007
A profile-driven statistical analysis framework for the design optimization of soft real-time applications · ESEC/SIGSOFT FSE 2007
Embedded and real-time systems
soft real-time systems
0.112007
A profile-driven statistical analysis framework for the design optimization of soft real-time applications · ESEC/SIGSOFT FSE 2007
Performance modeling and evaluation
workload characterization
0.112007
A profile-driven statistical analysis framework for the design optimization of soft real-time applications · ESEC/SIGSOFT FSE 2007
Performance modeling and evaluation
statistical analysis
0.012007
A profile-driven statistical analysis framework for the design optimization of soft real-time applications · ESEC/SIGSOFT FSE 2007

Methods — techniques the papers use, named apart from their topics

survey · 0.3simulation · 0.2hardware-software co-design · 0.2statistical analysis · 0.1offline profiling · 0.1context execution tree · 0.1
YearPublicationVenuePosition
2017 Traleika Glacier: A hardware-software co-designed approach to exascale computing
Vincent Cavé, Romain Cledat, Ankit More, Balasubramanian Seshasayee, Shekhar Borkar, Sanjay Chatterjee, Dave Dunning, Joshua B. Fryman
Parallel Comput.2
2017 Trends in Data Locality Abstractions for HPC Systems
abstract
The cost of data movement has always been an important concern in high performance computing (HPC) systems. It has now become the dominant factor in terms of both energy consumption and performance. Support for expression of data locality has been explored in the past, but those efforts have had only modest success in being adopted in HPC applications for various reasons. them However, with the increasing complexity of the memory hierarchy and higher parallelism in emerging HPC systems, locality management has acquired a new urgency. Developers can no longer limit themselves to low-level solutions and ignore the potential for productivity and performance portability obtained by using locality abstractions. Fortunately, the trend emerging in recent literature on the topic alleviates many of the concerns that got in the way of their adoption by application developers. Data locality abstractions are available in the forms of libraries, data structures, languages and runtime systems; a common theme is increasing productivity without sacrificing performance. This paper examines these trends and identifies commonalities that can combine various locality concepts to develop a comprehensive approach to expressing and managing data locality on future large-scale high-performance computing systems.
Didem Unat, Anshu Dubey, Torsten Hoefler, John Shalf, Mark James Abraham, Mauro Bianco, Bradford L. Chamberlain, Romain Cledat, H. Carter Edwards, Hal Finkel, Karl Fürlinger, Frank Hannig, Emmanuel Jeannot, Amir Kamil, Jeff Keasler, Paul H. J. Kelly, Vitus J. Leung, Hatem Ltaief, Naoya Maruyama, Chris J. Newburn, Miquel Pericàs
IEEE Trans. Parallel Distributed Syst.8
2013 Runnemede: An architecture for Ubiquitous High-Performance Computing
abstract
DARPA's Ubiquitous High-Performance Computing (UHPC) program asked researchers to develop computing systems capable of achieving energy efficiencies of 50 GOPS/Watt, assuming 2018-era fabrication technologies. This paper describes Runnemede, the research architecture developed by the Intel-led UHPC team. Runnemede is being developed through a co-design process that considers the hardware, the runtime/OS, and applications simultaneously. Near-threshold voltage operation, fine-grained power and clock management, and separate execution units for runtime and application code are used to reduce energy consumption. Memory energy is minimized through application-managed on-chip memory and direct physical addressing. A hierarchical on-chip network reduces communication energy, and a codelet-based execution model supports extreme parallelism and fine-grained tasks. We present an initial evaluation of Runnemede that shows the design process for our on-chip network, demonstrates 2-4x improvements in memory energy from explicit control of on-chip memory, and illustrates the impact of hardware-software co-design on the energy consumption of a synthetic aperture radar algorithm on our architecture.
Nicholas P. Carter, Aditya Agrawal, Shekhar Borkar, Romain Cledat, Howard David, Dave Dunning, Joshua B. Fryman, Ivan Ganev, Roger A. Golliver, Rob C. Knauerhase, Richard A. Lethin, Benoît Meister, Asit K. Mishra, Wilfred R. Pinfold, Justin Teller, Josep Torrellas, Nicolas Vasilache, Ganesh Venkatesh
HPCA4
2011 Enriching 3-D Video Games on Multicores
abstract
The introduction of multicore processors on desktops and other personal computing platforms has given rise to multiple interesting end-user application possibilities. One important trend is the increased presence of resource hungry applications like gaming and multimedia applications. One of the key distinguishing factors of these applications is that they are amenable to variable semantics (ie, multiple possibilities of results) unlike traditional applications wherein a fixed, unique answer is expected. For example, varying degrees of image processing improves picture quality, different model complexities used in game physics allow different degrees of realism during game play, and so on. The goal of this paper is to demonstrate that scalable semantics in applications such as video games can be enriched with optional tasks that can be launched and thus adapt to the amount of available resources at runtime. We propose a C/C++ API that allows the programmer to define how the current semantics of a program can be opportunistically enriched, as well as the underlying runtime system that orchestrates the different computations We show how this infrastructure can be used to enrich a well known game called Quake 3. Our results show that it is possible to perform significant enrichment without degrading the application's performance by utilizing additional cores.
Romain Cledat, Tushar Kumar, Jaswanth Sreeram, Santosh Pande
IPDPS1
2011 Efficiently speeding up sequential computation through the n-way programming model
abstract
With core counts on the rise, the sequential components of applications are becoming the major bottleneck in performance scaling as predicted by Amdahl's law. We are therefore faced with the simultaneous problems of occupying an increasing number of cores and speeding up sequential sections. In this work, we reconcile these two seemingly incompatible problems with a novel programming model called N-way. The core idea behind N-way is to benefit from the algorithmic diversity available to express certain key computational steps. By simultaneously launching in parallel multiple ways to solve a given computation, a runtime can just-in-time pick the best (for example the fastest) way and therefore achieve speedup.
Romain Cledat, Tushar Kumar, Santosh Pande
OOPSLA1
2010 Dynamic tuning of feature set in highly variant interactive applications
abstract
For important classes of interactive consumer applications, such as gaming and video, the Quality-of-Service requirement is to create a maximally immersive experience for the interactive user. This necessitates a trade-off between maximizing the computational complexity of application features versus the need to maintain a smooth and sufficiently high frame-rate. The implementation of these applications using conventional C/C++/Java development flows, their highly data-dependent time-varying nature, and the lack of analytical models for their execution time behavior pose unique challenges in obtaining significant QoS improvements.
Tushar Kumar, Romain Cledat, Santosh Pande
EMSOFT2
2007 RSTM : A Relaxed Consistency Software Transactional Memory for Multicores
Jaswanth Sreeram, Romain Cledat, Tushar Kumar, Santosh Pande
PACT2
2007 A profile-driven statistical analysis framework for the design optimization of soft real-time applications
abstract
Soft real-time applications lack a formal methodology for their design optimization. Well-established techniques from hard real-time systems cannot be directly applied to soft real-time applications, without losing key benefits of the soft real-time paradigm. We introduce a statistical analysis framework that is well-suited for discovering opportunities for optimization of soft real-time applications. We demonstrate how programmers can use the analysis provided by our framework to perform aggressive soft real-time design optimizations on their applications. The paper introduces the Context Execution Tree (CET) representation for capturing the statistical properties of function calls in the context of their execution in the program. The CET is constructed from an offline-profile of the application. Statistical measures are coupled with techniques that extract runtime distinguishable call-chains. This combination of techniques is applied to the CET to find statistically significant patterns of activity that i) expose slack in the execution of the application with respect to its soft real-time requirements, and ii) can be predicted with low overhead and high reliability during the normal execution of the application.
Tushar Kumar, Jaswanth Sreeram, Romain Cledat, Santosh Pande
ESEC/SIGSOFT FSE3