Timing model extractor builds a timing model of a digital circuit for use with a static timing analyzer. This paper proposes a novel method of generating a gray box timing model from gate-level netlist by reducing a timing graph. Previous methods of generating timing models sacrificed accuracy and/or did not scale well with design size. The proposed method is simple, yet it provides model accuracy including arbitrary levels of latch time borrowing and capability to support timing constraints that span multiple blocks. Also, cpu and memory resources required to generate the model scale well with size of the circuit. The generated model can provide a capacity improvement in timing verification by more than two orders of magnitude.

We propose a novel framework to solve the state assignment problem arising from the signal transition graph (STG) representation of an asynchronous circuit. We first establish a relation between STG's and finite state machines (FSM's). Then we solve the STG state assignment problem by minimizing the number of states in the corresponding FSM and by using a critical race-free state assignment technique. State signal transitions may be added to the original STG. A lower bound on the number of signals necessary to implement the STG is given. Our technique significantly increases the STG applicability as a specification for asynchronous circuits.>

We propose a novel method to eliminate dynamic hazards in asynchronous circuits synthesized from the signal transition graph (STG) specifications.We first review a relationship between syntactic constraints such as liveness and complete state coding at the STG level and the hazard properties at the gate level.Using this relationship, we identify the cause of dynamic hazards and rem,ove them by an iterative factoring method.Each factoring entails augmenting the given STG with an internal signal.This method is applicable to botb combinational and sequential circuits, and results in hazard-free multi-level implementations from STG specifications.

A description is given of SIS, an interactive tool for synthesis and optimization of sequential circuits. Given a state transition table or a logic-level description of a sequential circuit, SIS produces an optimized net-list in the target technology while preserving the sequential input-output behavior. Many different programs and algorithms have been integrated into SIS, allowing the user to choose among a variety of techniques at each stage of the process. It is built on top of MISII and includes all (combinational) optimization techniques therein as well as many enhancements. SIS serves as both a framework within which various algorithms can be tested and compared and as a tool for automatic synthesis and optimization of sequential circuits.>

The authors propose some syntactic and semantic extensions to a graphical specification called the signal transition graph (STG). They allow controlled-choice places to have fanout transitions of input signals and arbitrary Boolean expressions can be used as edge labels. They also allow one STG marking to represent more than one state. These extensions allow for a more natural and compact specification of asynchronous behavior. It is also shown that syntactic constraints on STGs are not sufficient to guarantee hazard-free implementations, and techniques are presented to synthesize hazard-free SOP, (sum of products) implementations under both SIC (single input change) and MIC (multiple input change) conditions. The synthesized circuits are speed-independent. They are hazard-free, independently of the gate delay variations, assuming that the circuit operates in fundamental mode.>