High performance and high quality for continuous media stream delivery needed by streaming server systems cannot be achieved efficiently using general-purpose operating systems, due to the overhead of the I/O mechanism implementation generally used. Special OS combined with powerful hardware can deliver better performance and quality but increases development complexity and deployment costs. The External I/O Engine Architecture adopts a hybrid approach, implementing streaming engines using the streaming-oriented Hi-Tactix operating system on inexpensive hardware, in combination with existing stream servers. The evaluation results of a QuickTime video server implemented with the existing Darwin Streaming Server using the External I/O Engine Architecture shows that Hi-Tactix can deliver 5 times the performance of a conventional OS and better stream quality, while keeping the amount of code necessary low.

A means of describing computer models on a high level and a means of generating the necessary data about the model for simulation are presented. The method is exemplified by using it to describe a RISC processor model. The debugging environment and interfaces for the simulator are presented. The use of the simulator to evaluate the performance of the HITAC M-880 multiprocessor system is reported.>

System requirements for VLSI technologies are reviewed and circuit technologies for BiCMOS VLSIs as computer elements are described. The following topics are dealt with: circuits for logic gates-conventional circuits and feedback type circuits for finer process; circuits for macrocells-CMOS logic circuits with bipolar sense circuits; and circuits for application-specific memories-sense amplifiers with comparators.>

The authors have developed the world's first BiCMOS 32-b single-chip microprocessor. It integrates 529 K transistors into a 12.98-mm/sup 2/ chip and typically realizes a 70-MHz frequency. The frequency is 1.5-2 times higher than that of current CMOS microprocessors. The microprocessor is designed to reduce the number of interchip communication signals in the critical path and to use basic cells optimally so as to allow fabrication into a single chip. The microprogram is divided into two parts, and frequently used microinstructions are stored in the ROM on the chip to reduce interchip communication. The translation lookaside buffer is also integrated in the microprocessor to reduce the interchip communication signals for memory access. Because of chip size and logic complexity constraints, less than 20% of the basic cells can be BiCMOS cells.>

To realize the highest performance possible for a sequential processor, and to realize utilization of a large amount of existing software, an integrated Prolog processor (IPP) and its optimized compiler are now being developed.