Abstract During the software development process, numerous bugs are reported daily in the software bug repositories. Bug triage assigned these bugs to the most relevant and expert developer for resolution. Moreover, assigning bugs to an incompetent or an over‐engaged developer causes repeated reassignment to other developers until it is resolved. This problem can be solved by devising a triage process that assigns bugs to not only expert developers but also to those who are either under‐engaged or reasonably engaged but are not over‐engaged in work. This paper has designed and implemented work engagement sensitive bug triage that resolves the issue of assigning bugs to developers considering their due work engagement, expertise as well as the current state of activity. For this purpose, a developer profile is built by using metrics to generate three types of scores: technical skill, work engagement and work experience. Metadata features like developer‐name, email, developer‐work‐experience in bug resolution, last and present‐work‐activity, timestamp, component and priority are used for it. A multi‐criteria‐based Henry–Garret technique is used to generate a single ranked list of developers from three ranked lists. The performance of the proposed approach is evaluated on four large OOS projects: Mozilla, Eclipse, Netbeans, and Open Office covering 895,439 bug reports accumulated for 33 years of development. The overall system accuracy of the proposed triage using all four datasets is 91.96 ± 0.05% which is 5.87% better than previously published work. The proposed method is achieved up to 90.30 ± 0.05 and 97.1 ± 0.05 MRR and accuracy of reassignment respectively that indicates how significantly it re‐assigns the bug to the relevant developers. The results demonstrate improvement in the accuracy of software‐bugs triaging as well as a reduction in the probability of bug‐tossing.

Cloud computing has proved to be a high-quality delivery paradigm over the past years. Some of the devices linked with the Cloud have weak security implications. The attacker can inject malware to disrupt the network and compromise the Cloud servers. An intrusion detection system (IDS) used to detect malicious activities in the network needs an improvement over the detection rate (DR) and false positive rate (FPR). In this article, a game-theoretic model has been devised to evaluate the attacker and the defender's strategies and assist the IDS in detecting the attack. The Nash equilibrium has been calculated using graphical methods to conclude the game. The proposed model is validated on real dataset using a machine learning stacked ensemble framework. With the proposed model, the results show an increase in the DR by 0.23, 0.03, and 0.05 percent, an increase in payoff by 0.22, 0.199, and 0.126 percent, a decrease in the FPR by 0.02, 0.03, and 0.07 percent of the IDS as compared to the other models.

Summary Long term evolution (LTE) mobile technology provides high data rate and low latency. 5G Technology is capable of handling the increasing number of IoT devices and provides ultra‐low latency, higher throughput, and higher reliability. Mobile edge computing (MEC) a key 5G technology strengthens the real‐time processing ability, releases the load on the Core Network, and helps in the real‐time processing of data, fulfilling the promise of high data rate and low latency. MEC is used to manage services efficiently to the near user resource. Using Osmotic Computing the services are efficiently scheduled and migrated. The work presented in this article proposes OCTRA‐5G Framework to effectively schedule services and allocate resources using Osmotic Computing (OC) by segregating the services into microservices and macroservices. The results are validated on the sets of 10, 20, and 30 gNBs (base stations) through simulation. OCTRA‐5G is tested on First Come First Serve (FCFS), Priority Scheduling (PS), and Shortest Job First (SJF) algorithm. FCFS provides less time complexity and higher throughput. The results presented using numerical simulations shows better performance by an average of 66.921% with OC than without OC.

Abstract A Wireless Sensor Network typically uses a large number of power‐constrained sensor nodes for sensing phenomenal data and for its processing. The lifetime of a sensor node is limited and this is a great challenge for researchers to sustain the network for a long time. Since, the data transmission from a sensor node to the base station is more power consuming, the hierarchical routing protocols play a major role in multihop communication and to prolong the network life time. It uses a clustering approach with an overhead of cluster head (CH) selection to attain this. This overhead needs proper addressing and to be reduced by some means. The work in this paper employs a new approach based on low‐energy adaptive clustering hierarchy (LEACH) and considers network load for electing CH in addition to number of links, residual sensor energy and distance. Here, energy and time are used for calculating load on a CH. The simulation results show that the proposed protocol performs better than LEACH, LEACH‐I, and NR‐LEACH algorithms on the parameters of average energy ratio throughput, end‐to‐end delay, packet delivery ratio, and a number of alive nodes.

Abstract The resource discovery on IoT paradigm requires to be efficient with respect to modeling, storage, processing, and validation of the gathered data. These requirements face challenges like interoperability, heterogeneity, etc, with respect to exponentially growing interconnected resources across distinct application domains and drastically changing search metrics. It leads resource discovery to emerge as a non‐linear constrained‐specific problem that need to be linearized for its optimization with reduced complexity. Keeping the perspective, a context‐aware search optimization framework on the internet of things is introduced, which targets knowledge presentation through schema, discovery via a multi‐modal search algorithm, and its optimization through an Iterative Gradient Descent algorithm. The multi‐modal search algorithm through keywords, value or spatial‐temporal indices performs resource discovery by finding the suited matches as a search set from a search‐space. The search set is further evaluated via the iterative gradient descent algorithm for optimization through the usage of iterative and convergence properties of the gradient descent. The search efficiency is tested using various objective functions and resources on MATLAB and is compared with Newton and Quasi‐Newton methods. The obtained results depict the efficiency of the algorithm graphically with reference to the searching time, such as validate the system performance.

In this paper, we propose a novel MOSFET parameter extraction method to enable early technology evaluation. The distinguishing feature of the proposed method is that it enables the extraction of MOSFET model parameters using limited and incomplete current–voltage measurements from on-chip monitor circuits. An important step in this method is the use of maximuma posterioriestimation where past measurements of transistors from various technologies are used to learn a prior distribution and its uncertainty matrix for the parameters of the target technology. The framework then utilizes Bayesian inference to facilitate extraction using a very small set of additional measurements. The proposed method is validated using various past technologies and post-silicon measurements for a commercial 28-nm process. The proposed extraction can be used to characterize the statistical variations of MOSFETs with the significant benefit that the restrictions imposed by the backward propagation of variance algorithm are relaxed. We also study the lower bound requirement for the number of transistor measurements needed to extract a full set of parameters for a compact model. Finally, we propose an efficient algorithm for selecting the optimal transistor biases by minimizing a cost function derived from information-theoretic concept of average marginal information gain.

In this paper, we propose a novel MOSFET parameter extraction method to enable early technology evaluation. The distinguishing feature of the proposed method is that it enables the extraction of an entire set of MOSFET model parameters using limited and incomplete IV measurements from on-chip monitor circuits. An important step in this method is the use of maximum-a-posteriori estimation where past measurements of transistors from various technologies are used to learn a prior distribution and its uncertainty matrix for the parameters of the target technology. The framework then utilizes Bayesian inference to facilitate extraction using a very small set of additional measurements. The proposed method is validated using various past technologies and post-silicon measurements for a commercial 28-nm process. The proposed extraction could also be used to characterize the statistical variations of MOSFETs with the significant benefit that some constraints required by the backward propagation of variance (BPV) method are relaxed.

In this paper, we propose a novel integrated circuits performance estimation algorithm through a physical subspace projection and maximum-a-posteriori (MAP) estimation. Our goal is to estimate the distribution of a target circuit performance with very small measurement sample size from on-chip monitor circuits. The key idea in this work is to exploit the fact that simulation and measurement data are physically correlated under different circuit configurations and topologies. First, different groups of measurements are projected to a subspace spanned by a set of physical variables. The projection is achieved by performing a sensitivity analysis of measurement parameters with respect to the subspace variables using a virtual source MOSFET compact model. Then a Bayesian treatment is developed by introducing prior distributions over these subspace variables. Maximum a posteriori estimation is then applied using the prior, and an expectation-maximization (EM) algorithm is used to estimate the circuit performance. The proposed method is validated by postsilicon measurement for a commercial 28-nm process. An average error reduction of 2x is achieved which can be translated to 32x reduction on data size needed for samples on the same die. A 150x and 70x sample size reduction on training dies is also achieved compared to traditional least-square fitting method and least-angle regression method, respectively, without reducing accuracy.

In this paper, we propose a methodology based on unsupervised learning for automatic clustering of wafer spatial signatures to aid yield improvement. Our proposed methodology is based on three steps. First, we apply sparse regression to automatically capture wafer spatial signatures by a small number of features. Next, we apply an unsupervised hierarchical clustering algorithm to divide wafers into a few clusters where all wafers within the same cluster are similar. Finally, we develop a modified L-method to determine the appropriate number of clusters from the hierarchical clustering result. The accuracy of the proposed methodology is demonstrated by several industrial data sets of silicon measurements.

In this paper, we propose a new technique to achieve accurate decomposition of process variation by efficiently performing spatial pattern analysis. We demonstrate that the spatially correlated systematic variation can be accurately represented by the linear combination of a small number of templates. Based on this observation, an efficient sparse regression algorithm is developed to accurately extract the most adequate templates to represent spatially correlated variation. In addition, a robust sparse regression algorithm is proposed to automatically remove measurement outliers. We further develop a fast numerical algorithm that may reduce the computational time by several orders of magnitude over the traditional direct implementation. Our experimental results based on both synthetic and silicon data demonstrate that the proposed sparse regression technique can capture spatially correlated variation patterns with high accuracy and efficiency.

Integrated circuits (ICs) must be robust to manufacturing variations. Circuit simulation at a set of worst case corners is a computationally efficient method for verifying the robustness of a design. This paper presents a new statistical methodology to determine the worst case corners for a set of circuit performances. The proposed methodology first estimates response surfaces for circuit performances as quadratic functions of the process parameters with known statistical distributions. These response surfaces are then used to extract the worst case corners in the process parameter space as the points where the circuit performances are at their minimum/maximum values corresponding to a specified tolerance level. Corners in the process parameter space close to each other are clustered to reduce their number, which reduces the number of simulations required for design verification. The novel concept of a relaxation coefficient to ensure that the corners capture the minimum/maximum values of all the circuit performances at the desired tolerance level is also introduced. The corners are realistic since they are derived from the multivariate statistical distribution of the process parameters at the desired tolerance level. The methodology is demonstrated with examples showing extraction of corners from digital standard cells and also the corners for analog/radio frequency (RF) blocks found in typical communication ICs.

In this paper we present an innovative methodology to estimate and improve the quality of analog and mixed-signal circuit testing. We first detect and reduce the redundancy in the electrical test measurements (e-tests), then we identify the e-test acceptability regions by considering performance specifications as well as process parameter distributions. Finally, we provide an effective metric for the accurate assessment of the parametric test coverage of embedded analog IP. Experimental results confirm the validity of the proposed methodology and its broad applicability to analog, mixed-signal and RF applications for different process technologies.

This paper presents a new statistical methodology to simulate the effect of both inter-die and intra-die variation on the electrical performance of analog integrated circuits. The main feature of this methodology is that it accounts for device mismatch by using a number of variables that is asymptotically constant in the limit of perfectly matching devices, and is typically close to the number of independent process factors normally used to account for inter-die process variations only. A unified model of process variation allows the effects of each source of variation and their joint impact to be estimated, thus providing designers more accurate analysis and variance optimization capability. State-of-the-art application examples demonstrate the accuracy and efficiency of this approach.