Demo Data from EDBT 2026 / reviewers in the wild / expert
Peter W. Wyatt
dblp:68/4754
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 2010
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Applied, interdisciplinary, general and emerging computing · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Integrated circuit design · 100% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design
digital circuit design |
0.1 | 1 | 2010 | FDSOI Process Technology for Subthreshold-Operation Ultralow-Power Electronics · Proc. IEEE 2010 |
Integrated circuit design
low-power circuit design |
0.1 | 1 | 2010 | FDSOI Process Technology for Subthreshold-Operation Ultralow-Power Electronics · Proc. IEEE 2010 |
Integrated circuit design › semiconductor device fabrication
process technology |
0.1 | 1 | 2010 | FDSOI Process Technology for Subthreshold-Operation Ultralow-Power Electronics · Proc. IEEE 2010 |
Integrated circuit design › low-power circuit design
subthreshold circuit design |
0.1 | 1 | 2010 | FDSOI Process Technology for Subthreshold-Operation Ultralow-Power Electronics · Proc. IEEE 2010 |
Methods — techniques the papers use, named apart from their topics
TCAD simulation · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2010 | FDSOI Process Technology for Subthreshold-Operation Ultralow-Power ElectronicsabstractUltralow-power electronics will expand the technological capability of handheld and wireless devices by dramatically improving battery life and portability. In addition to innovative low-power design techniques, a complementary process technology is required to enable the highest performance devices possible while maintaining extremely low power consumption. Transistors optimized for subthreshold operation at 0.3 V may achieve a 97% reduction in switching energy compared to conventional transistors. The process technology described in this article takes advantage of the capacitance and performance benefits of thin-body silicon-on-insulator devices, combined with a workfunction engineered mid-gap metal gate. Steven A. Vitale, Peter W. Wyatt, Nisha Checka, Jakub Kedzierski, Craig L. Keast |
Proc. IEEE | 2 |