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Giuseppe Gestri

dblp:68/529 · also G. Gestri · DBLP profile ↗
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7ranked-venue papers
3as first author
0since 2021 · last 1973
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Theory of computation · 5 · 2 first-authorSystems, architecture and hardware · 2 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
6 papers
Electronic design automation · 100%
Computer networks
1 paper
Physical-layer communications · 56% Network measurement and analytics · 44%

Topics — the 8 heaviest of 8, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › logic synthesis
sequential circuit synthesis
0.061972
Serial Realization of the Next State and Output Functions of a Sequential Machine · Inf. Control. 1972
Synthesis of Multiple Sequential Machines Having Different Inputs · IEEE Trans. Computers 1970
Sequential Machines with Less Delay Elements than Feedback Paths · IEEE Trans. Computers 1969
Electronic design automation
logic synthesis
0.021970
Synthesis of Multiple Sequential Machines Having Different Inputs · IEEE Trans. Computers 1970
Sequential Machines with Less Delay Elements than Feedback Paths · IEEE Trans. Computers 1969
Electronic design automation › logic synthesis
state assignment
0.021969
Sequential Machines with Less Delay Elements than Feedback Paths · IEEE Trans. Computers 1969
State Assignments for Reducing the Number of Delay Elements in Sequential Machines · Inf. Control. 1967
Physical-layer communications
modulation
0.011973
A Study of Integral Pulse Frequency Modulation of a Random Carrier · Inf. Control. 1973
Network measurement and analytics
per-flow measurement
0.011973
A Study of Integral Pulse Frequency Modulation of a Random Carrier · Inf. Control. 1973
Electronic design automation › logic synthesis › sequential circuit synthesis
machine decomposition
0.021968
Decomposition of a Synchronous Machine into an Asynchronous Submachine driving a Synchronous One · Inf. Control. 1968
Decomposition of Synchronous Sequential Machines into Synchronous and Asynchronous Submachines · Inf. Control. 1967
Physical-layer communications
signal processing for communications
0.011973
A Study of Integral Pulse Frequency Modulation of a Random Carrier · Inf. Control. 1973
Electronic design automation › design optimization
delay element minimization
0.021969
Sequential Machines with Less Delay Elements than Feedback Paths · IEEE Trans. Computers 1969
State Assignments for Reducing the Number of Delay Elements in Sequential Machines · Inf. Control. 1967

Methods — techniques the papers use, named apart from their topics

state splitting · 0.0partition theory · 0.0machine decomposition · 0.0common factor extraction · 0.0
YearPublicationVenuePosition
1973 A Study of Integral Pulse Frequency Modulation of a Random Carrier
Giuseppe Gestri
Inf. Control.1
1972 Serial Realization of the Next State and Output Functions of a Sequential Machine
Giuseppe Gestri
Inf. Control.1
1970 Synthesis of Multiple Sequential Machines Having Different Inputs
abstract
This note deals with the multiple realization of synchronous sequential machines for which the initial states are given. The results given by Smith and Kohavi, who have studied the problem for machines fed by the same input, are generalized to the case of machines having the same clock but different inputs. For these machines, a maximum common factor is defined, and it is shown how, if it exists, it can be obtained. The problem of internal state or input state splitting for machines that do not have a maximum factor and that are incomplete is not faced.
Giuseppe Gestri
IEEE Trans. Computers1
1969 Sequential Machines with Less Delay Elements than Feedback Paths
abstract
In this paper the possibility of removing in synchronous sequential machines some of the delay elements which store the internal state is discussed. Theorems and methods are given for eliminating all removable delay elements from a given realization of a synchronous machine and for selecting the assignments leading to a realization which requires the least number of delay elements. It is shown how the existence of these assignments is related to the existence of a pair of partitions on the set of states of the given machine. The internal performance of the sequential networks in which at least one but not all delay elements are removed is studied, and a "hybrid operating mode" is defined. A reclassification of sequential machines in terms of the algebraic structure of machines which relates to the number of removable delay elements is proposed. Sequential machines are, therefore, divided in three categories: synchronous, hybrid, and asynchronous, and some problems of decomposition for the three types of machines are discussed.
Giovanni Battista Gerace, Giuseppe Gestri
IEEE Trans. Computers2
1968 Decomposition of a Synchronous Machine into an Asynchronous Submachine driving a Synchronous One
Giovanni Battista Gerace, Giuseppe Gestri
Inf. Control.2
1967 State Assignments for Reducing the Number of Delay Elements in Sequential Machines
Giovanni Battista Gerace, Giuseppe Gestri
Inf. Control.2
1967 Decomposition of Synchronous Sequential Machines into Synchronous and Asynchronous Submachines
Giovanni Battista Gerace, Giuseppe Gestri
Inf. Control.2