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EDBT 2026 Demo / reviewers in the wild / expert

R. Damodaran

dblp:68/5354 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 1994
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 67% Integrated circuit design · 33%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › timing analysis
delay modeling		 0.011994
Delay models for CMOS, BiCMOS and BiNMOS circuits and their applications for timing simulations · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1994
Integrated circuit design
propagation delay		 0.011994
Delay models for CMOS, BiCMOS and BiNMOS circuits and their applications for timing simulations · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1994
Electronic design automation
timing analysis		 0.011994
Delay models for CMOS, BiCMOS and BiNMOS circuits and their applications for timing simulations · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1994

Methods — techniques the papers use, named apart from their topics

two-step iterative approach · 0.0alpha-power law model · 0.0
YearPublicationVenuePosition
1994 Delay models for CMOS, BiCMOS and BiNMOS circuits and their applications for timing simulations
abstract
In this paper, we report on delay models for CMOS, BiCMOS, and BiNMOS inverters. A two-step iterative approach has been adopted to account for the slope of the input waveforms. The Alpha-Power Law model equations have been used for the short-channel MOSFET's. The effects of high collector current on the base transit time and the current gain are also included in the models of the bipolar transistors. The developed delay models are incorporated in a timing simulator to estimate the propagation delay of chains with mixed CMOS/BiCMOS/BiNMOS gates. The estimates of the simulator deviate from those of HSPICE by less than 10%, while it is faster than HSPICE by two orders of magnitudes. Hence, it can be used for identifying critical paths in VLSI systems.>
Sherif H. K. Embabi, R. Damodaran
 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2
1993 An Accurate Delay Model for BiCMOS Gates and Off-chip Drivers
Sherif H. K. Embabi, R. Damodaran, R. Bhagwan, Don E. Ross
 ISCAS2