Internet content providers (e.g., video streaming, web services, file downloads) are increasingly deploying Peer-to-Peer Content Delivery Networks (PCDNs) to cache and distribute content by leveraging spare compute and storage resources at the network edge. This shift is primarily driven by the high costs associated with building and maintaining large-scale, centralized Content Delivery Network (CDN) architectures. A PCDN architecture can use multiple edge devices (e.g., access points, smart home gadgets) to distribute data in parallel to each client to increase the communication bandwidth and robustness to link/server failures. However, existing distributed multipath transport schedulers face significant challenges, such as Head-of-Line (HoL) blocking and Out-Of-Order (OOO) packet delivery, which can degrade multipath throughput to levels even lower than using a single path alone. In this paper, we introduce MPRD (Multipath Parallel Reverse Segment Download), a novel receiver-driven distributed transport protocol designed to overcome these limitations in PCDN architectures. MPRD is built on top of TCP and rethinks traditional multipath transport by using single-path TCP at each edge server. In MPRD, the client optimizes the starting point and direction of file segments to be downloaded by each single-path TCP connection in order to eliminate the inefficiencies of existing multipath schedulers. We implemented a prototype of MPRD in the Linux userspace and demonstrate that it significantly improves client throughput and reduces the CDN load (when the CDN is augmented by PCDN edge servers). We also evaluate MPRD’s performance in improving video delivery quality and show that it can substantially reduce the stalls and increase the PSNR visual quality by up to 35 dB.

Emerging mobile applications give rise to new bandwidth-hungry and latency-sensitive traffic classes that challenge existing wireless systems. Addressing them requires innovative approaches such as simultaneous data transmission across multiple Radio Access Technologies (RATs), e.g., WiFi and WiGig. However, existing transport layer multi-RAT traffic aggregation schemes, e.g., multi-path TCP, suffer from Head-of-Line (HoL) blocking and sub-optimal traffic splitting across the RATs that severely penalize their performance. In this paper, we investigate the design of FBDT, a novel multi-path transport layer solution that for the first time can achieve the sum of the throughput rates across the individual RATs network paths, despite their channel conditions' dynamics. We have implemented FBDT in the Linux kernel and show substantial improvement in throughput relative to state-of-the-art schemes, e.g, 2.5x gain in a dual-RAT scenario (WiFi and WiGig) when the client is mobile. Second, we extend FBDT to more than two radios and demonstrate that its throughput performance scales linearly with the number of RATs, in contrast to multi-path TCP, whose performance degrades with an increase in the number of RATs. We evaluate the performance of FBDT on different traffic classes and demonstrate: (i) 2-3 times shorter file download times, (ii) up to 10 times shorter streaming times and 10 dB higher video quality for progressive download video applications, and (iii) up to 9 dB higher viewport quality for interactive mobile VR applications, when our viewport quality maximization framework is employed along with FBDT.

The metaverse encompasses many virtual universes and relies on streaming high-quality 360° videos to VR/AR headsets. This type of video transmission requires very high data rates to meet the desired Quality of Experience (QoE) for all clients. Simultaneous data transmission across multiple Radio Access Technologies (RATs) such as WiFi and WiGig is a key solution to meet this required capacity demand. However, existing transport layer multi-RAT traffic aggregation schemes suffer from Head-of-Line (HoL) blocking and sub-optimal traffic splitting across the RATs, particularly when there is a high fluctuation in their channel conditions. As a result, state-of-the-art multi-path TCP (MPTCP) solutions can achieve aggregate transmission data rates that are lower than that of using only a single WiFi RAT in many practical settings, e.g., when the client is mobile. We make two key contributions to enable high quality mobile 360° video VR streaming using multiple RATs. First, we propose the design of FBDT, a novel multi-path transport layer solution that can achieve the sum of individual transmission rates across the RATs despite their system dynamics. We implemented FBDT in the Linux kernel and showed substantial improvement in transmission throughput relative to state-of-the-art schemes, e.g, 2.5x gain in a dual-RAT scenario (WiFi and WiGig) when the VR client is mobile. Second, we formulate an optimization problem to maximize a mobile VR client's viewport quality by taking into account statistical models of how clients explore the 360° look-around panorama and the transmission data rate of each RAT. We explore an iterative method to solve this problem and evaluate its performance through measurement-driven simulations leveraging our testbed. We show up to 12 dB increase in viewport quality when our optimization framework is employed.

Identifying whether the wireless channel between two devices (e.g., a base station and a client device) is Line-of Sight (LoS) or non-Line-of-Sight (nLoS) has many applications, e.g., it can be used in device localization. Prior works have addressed this problem, but they are primarily limited to sub6 GHz systems, assume sophisticated radios on the devices, incur additional communication overhead, and/or are specific to a single class of devices (e.g., a specific smartphone). In this paper, we address this channel classification problem for wireless devices with mmWave radios. Specifically, we show that existing beamforming training messages that are exchanged periodically between mmWave wireless devices can also be used in a deep learning model to solve the channel classification problem with no additional overhead. We then extend our work by developing a transfer learning model (t-LNCC) that is trained on simulated data, and can successfully solve the channel classification problem on any commercial-off-the-shelf (COTS) mmWave device with/without any real-world labeled data. The accuracy of t-LNCC is more than 95% across three different COTS wireless devices, when there is a small sample of labeled data for each device. We finally show the application of our classification problem in estimating the distance between two wireless devices, which can be used in localization.

Millimeter-wave (mmWave) systems use highly directional beams with narrow beamwidths to overcome the high path loss associated with their frequency bands. The use of narrow beams complicates the link establishment process as the transmitter and receiver need to search for appropriate beams before they can communicate with each other. Existing mmWave standards address the beam search process as part of the initial access (IA), and use contention based schemes that let multiple clients train their beams in the same search interval. However, there exists a severe power imbalance among competing clients' beams, as clients naturally have different orientations and are at different distances from the same access point. This beam power imbalance coupled with poor contention protocols results in poor IA fairness in dynamic systems with multiple clients. We propose a joint power control and contention adaptation protocol (coined JPOC) that addresses this unfairness problem. JPOC uses an open-loop and client-side power control mechanism that reduces the beam power imbalance among competing clients. It also uses a model-driven contention adaptation protocol that optimally adjusts the duration of the contention time according to the system dynamics. Comprehensive evaluation through a mixture of experiments and simulations show that compared to existing 802.11 ad/ay standards, JPOC substantially reduces the contention overhead and increases the IA fairness.

Floating point multiply-accumulate (FPMAC) unitis the backbone of modern processors and is a key circuit determining the frequency, power and area of microprocessors. FPMAC unit is used extensively in contemporary client microprocessors, further proliferated with ISA support for instructions like AVX and SSE and also extensively used in server processors employed for engineering and scientific applications. Consequently design of FPMAC is of vital consideration since it dominates the power and performance tradeoff decisions in such systems. In this work we demonstrate a novel FPMAC design which focuses on optimal computations in the critical path and therefore making it the fastest FPMAC design as of today in literature. The design is based on the premise of isolating and optimizing the critical path computation in FPMAC operation. In this work we have three key innovations to create a novel double precision FPMAC with least ever gate stages in the timing critical path: a) Splitting near and far paths based on the exponent difference (d=Exy-Ez = {-2, -1, 0, 1} is near path and the rest is far path), b) Early injection of the accumulate add for near path into the Wallace tree for eliminating a 3:2compressor from near path critical logic, exploiting the small alignment shifts in near path and sparse Wallace tree for 53 bit mantissa multiplication, c) Combined round and accumulate add for eliminating the completion adder from multiplier giving both timing and power benefits. Our design by premise of splitting consumes lesser power for each operation where only the required logic for each case is switching. Splitting the paths also provides tremendous opportunities for clock or power gating the unused portion (nearly 15-20%) of the logic gates purely based on the exponent difference signals. We also demonstrate the support for all rounding modes to adhere to IEEE standard for double precision FPMAC which is critical for employment of this design in contemporary processor families. The demonstrated design outperforms the best known silicon implementation of IBM Power6 [6] by 14% in timing while having similar area and giving additional power benefits due to split handling. The design is also compared to best known timing design from Lang et al. [5] and outperforms it by 7% while being 30% smaller in area than it.

OBJECTIVE: To study existing problem list terminologies (PLTs), and to identify a subset of concepts based on standard terminologies that occur frequently in problem list data. DESIGN: Problem list terms and their usage frequencies were collected from large healthcare institutions. MEASUREMENT: The pattern of usage of the terms was analyzed. The local terms were mapped to the Unified Medical Language System (UMLS). Based on the mapped UMLS concepts, the degree of overlap between the PLTs was analyzed. RESULTS: Six institutions submitted 76,237 terms and their usage frequencies in 14 million patients. The distribution of usage was highly skewed. On average, 21% of unique terms already covered 95% of usage. The most frequently used 14,395 terms, representing the union of terms that covered 95% of usage in each institution, were exhaustively mapped to the UMLS. 13,261 terms were successfully mapped to 6776 UMLS concepts. Less frequently used terms were generally less 'mappable' to the UMLS. The mean pairwise overlap of the PLTs was only 21% (median 19%). Concepts that were shared among institutions were used eight times more often than concepts unique to one institution. A SNOMED Problem List Subset of frequently used problem list concepts was identified. CONCLUSIONS: Most of the frequently used problem list terms could be found in standard terminologies. The overlap between existing PLTs was low. The use of the SNOMED Problem List Subset will save developmental effort, reduce variability of PLTs, and enhance interoperability of problem list data.

The advent of diminutive technology feature sizes has led to escalating transistor densities. Burgeoning transistor counts are casting a dark shadow on modern chip design: global interconnect delays are dominating gate delays and affecting overall system performance. Networks-on-Chip (NoC) are viewed as a viable solution to this problem because of their scalability and optimized electrical properties. However, on-chip routers are susceptible to another artifact of deep submicron technology, Process Variation (PV). PV is a consequence of manufacturing imperfections, which may lead to degraded performance and even erroneous behavior. In this work, we present the first comprehensive evaluation of NoC susceptibility to PV effects, and we propose an array of architectural improvements in the form of a new router design-called SturdiSwitch-to increase resiliency to these effects. Through extensive reengineering of critical components, SturdiSwitch provides increased immunity to PV while improving performance and increasing area and power efficiency.

Field-Programmable Gate Arrays (FPGAs) have been aggressively moving to lower gate length technologies. Such a scaling of technology has an adverse impact on the reliability of the underlying circuits in such architectures. Various different physical phenomena have been recently explored and demonstrated to impact the reliability of circuits in the form of both transient error susceptibility and permanent failures. In this work, we analyze the impact of two different types of hard errors, namely, Time- Dependent Dielectric Breakdown (TDDB) and Electromigration (EM) on FPGAs. We also study the performance degradation of FPGAs over time caused by Hot-Carrier Effects (HCE) and Negative Bias Temperature Instability (NBTI). Each study is performed on the components of FPGAs most affected by the respective phenomena, from both the performance and reliability perspective. Different solutions are demonstrated to counter each failure and degradation phenomena to increase the operating lifetime of the FPGAs.

Systems with the combined features of ASICs and field programmable gate arrays(FPGAs) are increasingly being considered as technology forerunners looking at their extraordinary benefits. This drags FPGAs into the technology scaling race along with ASICs exposing the FPGA industries to the problems associated with scaling. Extensive process variations is one such issue which directly impacts the profit margins of hardware design beyond 65 nm gate length technology. Since the resources in FPGAs are primarily dominated by the interconnect fabric, variations in the interconnect impacting the critical path timing and leakage yield needs rigorous analysis. In this work we provide a statistical modeling of individual routing components in an FPGA followed by a statistical methodology to analyze the timing and leakage distribution. This statistical model is incorporated into the routing algorithm to model a new statistically intelligent routing algorithm (SIRA), which simultaneously optimizes the leakage and timing yield of the FPGA device. We demonstrate and average leakage yield increase of 9% and timing yield by 11% using our final algorithm.

Aggressive scaling of technology has an adverse impact on the reliability of VLSI circuits. Apart from increasing transient error susceptibility, the circuits also become more vulnerable to permanent damage and failures due to different physical phenomenon. Such concerns have been recently demonstrated for regular micro-architectures. In this work we demonstrate the vulnerability of Field Programmable Gate Arrays (FPGA)s to two different types of hard errors, namely, Time Dependent Dielectric Breakdown (TDDB) and Electro-migration. We also analyze the performance degradation of FPGAs over time caused by Hot Carrier Effects (HCE). We also propose three novel techniques to counter such aging based failures and increase the lifetime of the device. Copyright 2006 ACM.

As FPGA designs in 65nm are being explored, reducing leakage power becomes an important design issue. A significant portion of the FPGA leakage is expended in the unused multiplexers used in the interconnect fabric. This work focuses on reducing the leakage of these unused multiplexers by controlling their inputs. We investigate the design issues involved in implementing such a technique and also show experimental results demonstrating the effectiveness of our approach.

We provide a methodology to perform both bus partitioning and bus frequency assignment to each of the bus segments simultaneously while optimizing both the power consumption and performance of the system. We use a genetic algorithm and design an appropriate cost function which optimizes the solution on the basis of its power consumption and performance. The evaluation of our approach using a set of multiprocessor applications shows an average reduction of the energy consumption by 60% over a single shared bus architecture. Our results also show that it is beneficial to assign bus frequencies and perform bus partitioning simultaneously, instead of performing them sequentially.

OBJECTIVE: The integration of SNOMED CT into the Unified Medical Language System (UMLS) involved the alignment of two views of synonymy that were different because the two vocabulary systems have different intended purposes and editing principles. The UMLS is organized according to one view of synonymy, but its structure also represents all the individual views of synonymy present in its source vocabularies. Despite progress in knowledge-based automation of development and maintenance of vocabularies, manual curation is still the main method of determining synonymy. The aim of this study was to investigate the quality of human judgment of synonymy. DESIGN: Sixty pairs of potentially controversial SNOMED CT synonyms were reviewed by 11 domain vocabulary experts (six UMLS editors and five noneditors), and scores were assigned according to the degree of synonymy. MEASUREMENTS: The synonymy scores of each subject were compared to the gold standard (the overall mean synonymy score of all subjects) to assess accuracy. Agreement between UMLS editors and noneditors was measured by comparing the mean synonymy scores of editors to noneditors. RESULTS: Average accuracy was 71% for UMLS editors and 75% for noneditors (difference not statistically significant). Mean scores of editors and noneditors showed significant positive correlation (Spearman's rank correlation coefficient 0.654, two-tailed p < 0.01) with a concurrence rate of 75% and an interrater agreement kappa of 0.43. CONCLUSION: The accuracy in the judgment of synonymy was comparable for UMLS editors and nonediting domain experts. There was reasonable agreement between the two groups.

Soft errors that change configuration bits of an SRAM based FPGA modify the functionality of the design. The proliferation of FPGA devices in various critical applications makes it important to increase their immunity to soft errors. In this work, we propose the use of an asymmetric SRAM (ASRAM) structure that is optimized for soft error immunity and leakage when storing a preferred value. The key to our approach is the observation that the configuration bitstream is composed of 87% of zeros across different designs. Consequently, the use of ASRAM cell optimized for storing a zero (ASRAM-0) reduces the failure in time by 25% as compared to the original design. We also present an optimization that increases the number of zeros in the bitstream while preserving the functionality.