Fixing bugs in hardware design code has become a challenging task due to the increasing complexity of modern circuit designs. As a result, automated program repair techniques have been proposed to synthesize patches for bugs in hardware designs and achieved promising results. However, existing techniques are still limited in synthesizing expressions for complex bugs. In this work, we explore the possibility of addressing complex bugs by proposing SREPAIR, a novel symbolic regression-based repair technique. The key novelty of SREPAIR lies in three aspects: 1) we propose a novel expression modification encoding that enables fine-grained adjustments to buggy expressions. 2) we introduce expression synthesis-based templates that allow for flexible and expressive repairs. 3) we develop a novel symbolic regression network-based synthesis algorithm that effectively synthesizes complex expressions. Experimental results on the four peer-reviewed datasets demonstrate that SREPAIR correctly fixes 56 bugs out of 112 bugs, which achieves 43.6% and 194.7% improvement over the previous state-of-the-art RTL-REPAIR (39 bugs) and CIRFIX (19 bugs). To evaluate the generalizability of SREPAIR, we further construct an augmented dataset of 282 bugs by mutating hardware designs. SREPAIR shows its better generalizability by correctly fixing 127 bugs, reaching 217.5% improvement over the best approach.

Complexity of cryptographic algorithm renders verification of cryptographic hardware design vulnerable to the oracle problem. We propose Minoan: the first opensource verification framework based on Metamorphic testing for cryptographic hardware design to mitigate the oracle problem. Minoan constructs six metamorphic relationships for cryptographic hardware design verification based on domain knowledge, and further designs the time-aware metamorphic relationship satisfiability checking mechanism to strengthen the integration of metamorphic testing with cryptographic hardware. Finally, the evaluation on public datasets from OpenCores shows that Minoan achieves promising results with detecting up to ${9 8 . 0 2 \%}$ bugs.

Verification of hardware design code is crucial for the quality assurance of hardware products. Being an indispensable part of verification, localizing bugs in the hardware design code is significant for hardware development but is often regarded as a notoriously difficult and time-consuming task. Thus, automated bug localization techniques that could assist manual debugging have attracted much attention in the hardware community. However, existing approaches are hampered by the challenge of achieving both demanding bug localization accuracy and facile automation in a single method. Simulation-based methods are fully automated but have limited localization accuracy, slice-based techniques can only give an approximate range of the presence of bugs, and spectrum-based techniques can also only yield a reference value for the likelihood that a statement is buggy. Furthermore, formula-based bug localization techniques suffer from the complexity of combinatorial explosion for automated application in industrial large-scale hardware designs. In this work, we propose Kummel, a K nowledge-a u g m ented m utation-bas e d bug loca l ization for hardware design code to address these limitations. Kummel achieves the unity of precise bug localization and full automation by utilizing the knowledge augmentation through mutation analysis. To evaluate the effectiveness of Kummel, we conduct large-scale experiments on 76 versions of 17 hardware projects by seven state-of-the-art bug localization techniques. The experimental results clearly show that Kummel is statistically more effective than baselines, e.g., our approach can improve the seven original methods by 64.48% on average under the RImp metric. It brings fresh insights of hardware bug localization to the community.

The verification of hardware design code is a critical aspect in ensuring the quality and reliability of hardware products. Finding bugs in hardware design code is important for hardware development and is frequently considered as a notoriously challenging and time-consuming activity while being an essential aspect of verification. Thus, bug localization techniques that could assist manual debugging have attracted much attention in the hardware community. However, there exists an unpredictable time span between the precise origin of a bug and its detected manifestation in prior work without costly formal verification. Locating the bug responsible for the exposed discrepancy between expected and exhibited design behavior remains a major challenge. In this work, we propose Tartan, a T ime- a ware spect r um-based bug localiza t ion with d a ta purificatio n for hardware design code to address these limitations. Tartan integrates hardware-specific timing information with the spectrum and captures the changes of executed statements when the state of the circuit changes to effectively locate bugs. Further, Tartan purifies the spectrum data from the simulation and evaluates the suspiciousness of the statements in the design to indicate the likelihood of being buggy. To evaluate the effectiveness of Tartan, we conduct large-scale experiments on 69 versions of 15 hardware projects by the state-of-the-art bug localization techniques. The experimental results clearly show that Tartan is statistically more effective than the baselines. It provides a new perspective on hardware design code bug localization and brings fresh insights to the community.

Hardware description languages (HDLs) are pivotal for the development of hardware designs. The programming courses for HDLs are also popular in both universities and online course platforms. Similar to programming assignments of software languages (SLs), these of HDLs also actively call for automated program repair (APR) techniques to provide personalized feedback for students. However, the research of APR techniques targeting HDL programming assignments is still in an early stage. Due to the significantly different programming mechanism of HDLs from SLs, the only APR technique (i.e., CirFix) targeting HDL programming assignments contributes a customized repair pipeline. However, the fundamental challenges in the design of HDL-oriented fault localization and patch generation still remain unresolved. In this work, we propose a signal value transition-guided defect repair technique named STRIDER by capturing the intrinsic features of HDLs. This technique consists of a time-aware dynamic defect localization approach to precisely localize defects, and a signal value transition-guided patch synthesis approach to effectively generate fixes.We further construct a dataset of 57 real defects from HDL programming assignments for tool evaluation. The evaluation reveals the overfitting issue of the pioneering tool CirFix and the significant improvement of STRIDER over CirFix in terms of both effectiveness and efficiency. In particular, STRIDER is more effective by correctly fixing 2.3X as many defects as CirFix in the real defect dataset, and is 23X more efficient by generating a correct fix within five minutes on average in the synthetic defect dataset, while CirFix takes around two hours on average.

Mutation testing, a well-suited technology for functional validation, is regrettably poorly studied in hardware. We propose Mantra: the first open-source code-level mutation testing tool based on real hardware bugs. Specifically, Mantra devises time-aware mutation killing mechanism for cost reduction of hardware mutation testing using the parallelism of hardware design code, and then defines and implements 19 hardware mutation operators via large-scale empirical analysis on real bugs. Finally, the evaluation on public datasets from CirFix and OpenCores shows that Mantra achieves promising results with a maximum boost of 83.44%.

Automated program repair (APR) is being leveraged in hardware description languages (HDLs) to fix hardware bugs without human involvement. Most existing APR techniques search for donor code (i.e., code fragment for bug fixing) in the original program to generate repairs, which is based on the assumption that donor code can be found in existing source code. The redundancy assumption is the fundamental basis of most APR techniques, which has been widely studied in software by searching code clones of donor code. However, despite a large body of work on code clone detection, researchers have focused almost exclusively on repositories in traditional programming languages, such as C/C++ and Java, while few studies have been done on detecting code clones in HDLs. Furthermore, little attention has been paid on the repetitiveness of bug fixes in hardware designs, which limits automatic repair targeting HDLs. To validate the redundancy assumption for HDL, we perform an empirical study on code clones of real-world bug fixes in Verilog. On top of empirical results, we find that 17.71% of newly introduced code in bug fixes can be found from the clone pairs of buggy code in the original program, and 11.77% can be found in the file itself. The findings not only validate the assumption but also provides helpful insights for the design of APR targeting HDLs.

Verification of hardware design code is crucial for the quality assurance of hardware products. As an indispensable part of verification, localizing faults in the hardware design code is significant for hardware development but is often regarded as a notoriously difficult and time-consuming task. Thus, automated fault localization techniques that could assist manual debugging have attracted much attention in the hardware community. Prior work indicates that existing methods neither fully utilize program dynamic execution information nor lack attention to timing. In this work, we propose Tarsel: a time-aware spectrum-based fault localization approach to help bridge this gap. Tarsel integrates hardware-specific timing information with the program spectrum and captures the changes of executed statements when the state of the hardware program changes to effectively locate faults. The experimental results show that Tarsel successfully locates over half of bugs in the benchmark at Top-3 and about 90% of bugs at Top-5. In addition, Tarsel statistically outperforms the state-of-the-art fault localization approach CirFix under all six typical metrics. In particular, while no bugs are ranked at Top-1 by CirFix, Tarsel successfully locates 11.41% of bugs at Top-1. It brings fresh insights of hardware bug localization to the community.

Traditional methods include iterative compilation can make the compilation optimization sequence selection process automatically, and execute as many different versions of the program as possible within the allowed time and space. However, this method is a mechanical search. It lacks the use of previously acquired experience and requires larger implementation overhead. Therefore, there is a need for a compilation optimization method that can automatically predict the reliability of the target program after transformation without actually running the program. This paper proposes a method for compilation optimization sequence generation: ROPO (reliability oriented phase ordering) ANN. This method extracts program features based on the LLVM compilation framework and searches the compilation optimization space to find the best compilation optimization sequence for the current program version. The experimental results show that when comparing ROPOANN with existing iterative compilation methods and the non-iterative generation algorithms, the reliability improvement has also been greatly improved.

Modern compilers provide a huge number of optional compilation optimization options. Not only the selection of compilation optimization options represents a hard problem to be solved, but also the ordering of the phases is adding further complexity, making it a long standing problem in compilation research. A large number of experiments have shown that different ordering of the phases has varying degrees of influence on the program. Currently, most research focuses on the traditional optimization goals, such as execution speedup and code size optimization. In this paper, we focus on the impact of the phase-ordering on program reliability. We propose a new model with reinforcement learning algorithm A3C for finding the phase order that can improve the reliability of the program. We performed our experiments with LLVM compiler framework, considering 130 LLVM optimization options. The experimental results show that when compared with LLVM standard options and the existing phase-ordering method with genetic algorithm, the phase order found by our model can bring higher reliability gain to the program.

Modern compilers provide a huge number of optional compilation optimization options. It is necessary to select the appropriate compilation optimization options for different programs or applications. To mitigate this problem, machine learning is widely used as an efficient technology. How to ensure the integrity and effectiveness of program information is the key to problem mitigation. In addition, when selecting the best compilation optimization option, the optimization goals are often execution speed, code size, and CPU consumption. There is not much research on program reliability. This paper proposes a Gate Graph Attention Neural Network (GGANN)-based compilation optimization option selection model. The data flow and function-call information are integrated into the abstract syntax tree as the program graph-based features. We extend the deep neural network based on GGANN and build a learning model that learns the heuristics method for program reliability. The experiment is performed under the Clang compiler framework. Compared with the traditional machine learning method, our model improves the average accuracy by 5–11% in the optimization option selection for program reliability. At the same time, experiments show that our model has strong scalability.