In this paper, the feasibility of using register banks as a top of stack (TOS) buffer is demonstrated. A quantitative performance evaluation is made of three automatic TOS buffer management algorithms: a simple single pointer algorithm, an intelligent single pointer algorithm, and a sophisticated double pointer algorithm. An automatically managed TOS buffer can effectively cache local data accesses resulting in a large memory traffic reduction. Results demonstrate that a small (with respect to the size of the benchmark data set) TOS buffer provides a very high data reference hit ratio and requires minimal processor intervention for TOS buffer management. The simple single pointer algorithm is shown to provide the best overall performance for various metrics including memory bandwidth, TOS buffer hit ratio, processor intervention, and processor execution speed.

Rule-based systems, on the surface, appear to be capable of exploiting large amounts of parallelism—it is possible to match each rule to the data memory in parallel. In practice, however, we show that the speed-up from parallelism is quite limited, less than 10-fold. The reasons for the small speed-up are: (1) the small number of rules relevant to each change to data memory; (2) the large variation in the processing required by the relevant rules; and (3) the small number of changes made to data memory between synchronization steps. Furthermore, we observe that to obtain this limited factor of 10-fold speed-up, it is necessary to exploit parallelism at a very fine granularity. We propose that a suitable architecture to exploit such fine-grain parallelism is a bus-based shared-memory multiprocessor with 32-64 processors. Using such a multiprocessor (with individual processors working at 2 MIPS), it is possible to obtain execution speeds of about 3800 rule-firings/sec. This speed is significantly higher than that obtained by other proposed parallel implementations of rule-based systems.

This paper presents a technique for specifying change of control (e.g. branch) commands at a sequential processor's macroinstruction set level. It is shown that by representing high level language (HLL) control statements with special machine language instructions, the usual delays associated with control flow changes can be reduced. Preserving the HLL control flow information increases performance by reducing both the number of executed branches and pipeline breaks.