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Brian J. Henz

dblp:68/890 · DBLP profile ↗
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3ranked-venue papers
0as first author
0since 2021 · last 2014
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
GPUs and heterogeneous computing · 44% Hardware accelerators and domain-specific architectures · 44% Embedded and real-time systems · 13%

Topics — the 3 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
GPUs and heterogeneous computing
CPU-GPU heterogeneous computing
0.112011
Hybrid Core Acceleration of UWB SIRE Radar Signal Processing · IEEE Trans. Parallel Distributed Syst. 2011
Hardware accelerators and domain-specific architectures › signal processing accelerator
radar signal processing accelerator
0.112011
Hybrid Core Acceleration of UWB SIRE Radar Signal Processing · IEEE Trans. Parallel Distributed Syst. 2011
Embedded and real-time systems
real-time signal processing
0.012011
Hybrid Core Acceleration of UWB SIRE Radar Signal Processing · IEEE Trans. Parallel Distributed Syst. 2011

Methods — techniques the papers use, named apart from their topics

brook+ · 0.1CUDA · 0.1
YearPublicationVenuePosition
2014 A Class-Structured Approach to Couple Application and Hybrid Core Parallelism
abstract
This paper presents an application that performs multi-objective geospatial optimizations for tactical mission planning in an urban environment. Utilizing a XML-driven C++ framework developed for hybrid platforms, the application distributes computational tasks to a collection of heterogeneous OpenCL devices and achieves efficient task parallel scaling. The framework abstracts the details of the mission scenario setup, compute device architecture details, and task scheduling to enable robust extensibility in software. Performance scalability and multi-objective parameter visualization for a prototypical mission scenario are documented in this study.
James A. Ross, David A. Richie, Song Jun Park, Dale R. Shires, Brian J. Henz
PDP5
2012 Taming Wild Horses: The Need for Virtual Time-Based Scheduling of VMs in Network Simulations
abstract
The next generation of scalable network simulators employ virtual machines (VMs) to act as high-fidelity models of traffic producer/consumer nodes in simulated networks. However, network simulations could be inaccurate if VMs are not scheduled according to virtual time, especially when many VMs are hosted per simulator core in a multi-core simulator environment. Since VMs are by default free-running, on the outset, it is not clear if, and to what extent, their untamed execution affects the results in simulated scenarios. Here, we provide the first quantitative basis for establishing the need for generalized virtual time scheduling of VMs in network simulators, based on an actual prototyped implementations. To exercise breadth, our system is tested with disparate applications: (a) a set of message passing parallel programs, (b) a computer worm propagation phenomenon, and (c) a mobile ad-hoc wireless network simulation. We define and use error metrics and benchmarks in scaled tests to empirically report the poor match of traditional, fairness-based VM scheduling to VM-based network simulation, and also clearly show the better performance of our simulation-specific scheduler, with up to 64 VMs hosted on a 12-core simulator node.
Srikanth B. Yoginath, Kalyan S. Perumalla, Brian J. Henz
MASCOTS3
2011 Hybrid Core Acceleration of UWB SIRE Radar Signal Processing
abstract
To move High-Performance Computing (HPC) closer to forward operating environments and missions, the Army Research Laboratory is developing approaches using hybrid, asymmetric core computing. By blending capabilities found in Graphics Processing Units (GPUs) and traditional von Neumann multicore Central Processing Units (CPUs), approaches are being developed and optimized to provide at or near real-time processing speeds for research project applications. Algorithms are designed to partition work to resources best designed to handle the processing load. The use of commodity resources allows the design to be flexible throughout the life cycle without the costly and time-consuming delays associated with Application-Specific Integrated Circuit (ASIC) development. This paradigm allows for rapid technology transfer to end users. In this paper, we describe a synchronous impulse reconstruction radar imaging algorithm that has been designed for hybrid CPU-GPU processing. We discuss various optimizations such as asynchronous task partitioning between the CPU and GPU as well as data movement reduction. We also discuss analysis and design of the algorithms within the context of two programming models: NVIDIA's CUDA and AMD's ATI Brook+. Finally, we report on the speedup achieved by this approach that allowed us to take a code once restricted to postprocessing and transform it into one that exceeds real-time performance requirements.
Song Jun Park, James A. Ross, Dale R. Shires, David A. Richie, Brian J. Henz, Lam H. Nguyen
IEEE Trans. Parallel Distributed Syst.5