Nonvolatile SRAM (nvSRAM), which integrates the nonvolatile elements with SRAM using a direct bit-to-bit connection has raised much attention in the past few years, owing to its fast parallel data transfer and fast power-on/off speed. However, few nvSRAM macros have been silicon verified to be enacted through the power-failure event. On the other hand, the capacity of fabricated nvSRAM macro is small (~ Kbit) to date, inhibiting its practical application. This study presents a novel ReRAM-based nvSRAM bitcell with improved reliability and scalability. A 64KB nvSRAM macro was designed and integrated into a 32-bit microcontroller unit (MCU). The chip was fabricated using HfOx-based BEOL ReRAM and a 130nm CMOS technology. To pursue fast storage, a write-without-verify scheme is adopted to program ReRAM, measurement results show that the raw bit error rate between the power outages is < 0.1% for the full macro under such constraint. Cryptography and machine learning applications are successfully performed on the MCU system. For the first time, with the help of correction techniques, we achieved an error-free nvSRAM macro that is reliable enough to store/restore programs and demonstrated a real-time robotic control system empowered by the nvSRAM. The proposed nvSRAM macro has the largest capacity to date.

SSDs are getting widely used in data centers. It is a critical issue to design efficient software for exploiting the benefits of fast SSD hardware. In this paper, we propose OCStore, an object store based on open-channel SSDs for distributed object storage system. OCStore manages the objects directly on raw flash memory, mitigating redundant functions across the object store, the file system, and the FTL layers. It provides streamed transactional update, which not only ensures the multi-page atomicity leveraging the non-overwrite flash write features, but also provides isolation for independent I/O streams while enabling parallel accesses to different channels. OCStore also coordinates different channels to enable transaction-aware scheduling, so as to reduce transaction-level latency and provide low response time to distributed storage. We implement OCStore in Linux kernel on the real open-channel SSDs, and evaluate them as OSDs in Ceph. Evaluations show that OCStore outperforms state-of-the-art object stores by 1.5× to 3.0×, while providing much lower and stable latencies, and decreases up to 70% write traffic under heavy workloads.

In this paper, an ultra-low-power area-efficient 12-bit extended counting analog-to-digital conversion (EC-ADC) is presented. A double-sampling configuration for incremental ΣΔ modulators is proposed to halve the clock frequency of EC-ADC for the same conversion accuracy and rate. A class-AB operational transconductance amplifier (OTA) for low power EC-ADC is developed. The proposed architecture has been implemented using a commercial 0.18μm CMOS technology and occupies an area of 0.036mm2. Measured results show that a power consumption of 13μW can be achieved at the conversion rate of 50Ksamples/s and 10.2-bit accuracy respectively.

Dual supply voltage was a mature method to reduce the dynamic power of specific and programmable circuits, and the unsettled low voltage level (VL) was proved to have impact on its effect. In this paper, a circuit-level power model is developed to estimate the optimal VLfast for field-programmable gate array (FPGA). The model is mainly based on the path delay distribution of applications and the delay function of the integrated circuit technology. It can also count minor factors, such as path overlap, transition density, and capacitance. Experiment was conducted on a 90-nm FPGA model using MCNC benchmark. The results showed that the proposed method could generate near optimum VLfor most benchmarks. The best power reduction ratio is only 5.6% less than the gate-level heuristic method, which is relatively precise, but our method is ~100-10000 times faster. It implies that the dual voltage design with variable VL is a possible and promising low power method for field-programmable devices.

Dual-VDD FPGA architecture has been proposed to reduce the FPGA's power consumption, where a low VDD (VDDL) is assigned to non-critical resources and unused resources are power-gated. In this paper, a path-delay-distribution (PDD) based design method of supply voltage in dual-VDD FPGA is developed, which gives an estimated optimal VDD solution for the required applications. Meanwhile, an improved tree-based VDD assignment algorithm is accordingly designed. Thus chip-level optimization of dual-VDD FPGA is achieved on the chosen granularity with the power consumption minimized. Based on MCNC benchmark circuits at 90nm technology node, our experimental result shows that: the power reduction rate depends on VDDL level; the design method proposed in this work gives the optimal one automatically. This design method could be utilized to guide the FPGA automatic design, saving the time to search for the system's optimal supply voltage, and the proposed assignment algorithm is more efficient in dynamic power reduction.

A novel high-speed and low-power negative level shifter suitable for low voltage applications is presented. To reduce the switching delay and leakage current, a novel bootstrapping technique is designed for the level shifter. Furthermore, a pull-down driver is proposed to have high driving capability under different operation modes. The circuit has been designed in 130 nm 1.5 V/5 V triple-well CMOS technology with a nominal power supply VDDof 1.5 V and a negative voltage of -4.5 V. Simulation results show that the switching delay and power consumption have been significantly reduced by roughly 62% and 65%, respectively. In addition, the proposed level shifter realizes a wide operation margin with a lower VDDcompared to conventional implementations.