Factorization of large semiprimes remains one of the most challenging problems for classical computers. Shor’s algorithm offers a quantum approach that reduces computational complexity, but its practical application is currently limited by hardware constraints. Meanwhile, as a provisional approach, quantum annealing (QA) has been explored through formulations of the quadratic unconstrained binary optimization (QUBO) problem. Among existing methods, the blockwise partial-product approach effectively reduced the QUBO variable count but was limited to semiprimes up to 21 bits. To extend factorization to larger semiprimes, this paper addresses key engineering challenges in constructing efficient QUBO formulations for prime factorization. We propose five techniques to reduce variable counts and improve scalability with current QA hardware: (1) dividing the problem into subproblems with partial constraints; (2) applying analytical reductions near the LSB; (3) applying analytical reductions near the MSB; (4) exploiting special patterns in semiprimes, with odd bit widths and long MSB-side zero sequences; and (5) balancing variable usage across both sides of the subproblem. Integrated into a QUBO converter, these methods enable stable factorization of semiprimes up to 47-bits within 20 seconds and can extend to special 2049-bit instances with 1001 consecutive MSB-side zeros.

A true random number generator (TRNG) is a fundamental component of hardware security. Latch-based TRNGs (LTRNGs), with their simple circuitry, are well-suited for energy-constrained IoT devices. However, a mismatch between the two inverters in the latch can result in little or no entropy output. This work presents chip measurement results demonstrating the use of negative bias temperature instability (NBTI) to mitigate mismatch in LTRNG. We propose a sequence to quantify the initial mismatch and selectively applying NBTI stress to PMOS device with higher conductivity for the first time. Measurement results in a 130nm CMOS process show that after 1000 minutes of NBTI stress at 3.0 V/120°C, the mismatches are reduced to within the overcompensated target of ±20 mV, and the output entropy improves from zero to over 0.85. Mismatch recovery at 20°C is negligible. Recovery at 120°C is accelerated, with mismatches still remaining below 50% of their initial values, and the output entropy remaining at 0.47 and 0.80 for the measured two chips. The randomness of post-processed data is validated using NIST SP 800-22 and SP 800-90B.

Conventional quantum error correction (QEC) de-coders such as Minimum-Weight Perfect Matching (MWPM) and Union-Find (UF) offer high thresholds and fast decoding, respectively, but both suffer from high topological complexity. In contrast, Ising model-based decoders reduce topological complexity but demand considerable decoding time. We propose the Symmetric One-Hot Matching Elector (SOME), a novel decoder that reformulates the QEC decoding task as a Quadratic Unconstrained Binary Optimization (QUBO) problem—termed the One-Hot QUBO (OHQ). Each variable in the QUBO represents whether a given pair of flipped syndromes is matched, while the error probabilities between the pair are encoded as interaction coefficients (weight). Constraints ensure that each flipped syndrome is matched exactly once. Valid solutions of OHQ correspond to self-inverse permutation matrices, characterized by symmetric one-hot encoding. To solve the OHQ efficiently, SOME reformulates the decoding task as the construction of permutation matrices that minimize the total weight. It initializes each candidate matrix from one of the minimum-weight syndrome pairs, then iteratively appends additional pairs in ascending order of weight, and finally selects the permutation matrix with the lowest total energy. SOME achieves up to a 99.9x reduction in variable count and reduces decoding times from milliseconds to microseconds on a single-threaded commodity CPU. OHQ also maintains performance up to a 10.5% physical error rate, surpassing the highest known threshold of MWPM.

True random number generators (TRNGs) are commonly used in hardware security for secure authentication, data encryption, etc. The raw random numbers often exhibit defects. The most commonly observed defects are bias and correlations. Post processing techniques have been developed to address them. The von Neumann method addresses bias, but it requires input that is uncorrelated and has an identical distribution. On the other hand, the Markov chain can address correlation but introduce bias. In this work, we research the lightweight combination of two techniques. We verified that MKV2(QL4)/VN2 performs well for both Markov and non-Markov model bitstreams. MKV1(QL8)/VN8W is effective for the Markov model. The randomness is verified by NIST SP 800-22 and 800-90B, and ENT, respectively. Both of these circuits require only 16 bits of memory, which is 12 times smaller than in previous work. MKV1(QL8)/VN8W is implemented using 65-nm CMOS. A prototype chip demonstrates a minimum energy consumption of 0.149 pJ/bit at 0.45V. When applied to a latch-based TRNG, it can double the operation frequency thanks to the enhanced decorrelation. The total energy consumption is reduced by 21%.

For the 7-nm technology node, cell placement with a drain-to-drain abutment (DDA) requires additional filler cells, increasing the placement area. This is the first work to fully automatically synthesize a DDA-aware cell library with the optimized number of drains on cell boundary based on ASAP 7-nm PDK. We propose a DDA-aware dynamic programming-based transistor placement. Previous works ignore the use of the M0 layer in cell routing. We first propose an ILP-based M0 routing planning. With M0 routing, the congestion of M1 routing can be reduced and the pin accessibility (PA) can be improved due to the diminished use of M2 routing. We also present a quadratic-programming based-coupling-capacitance-aware initial routing to optimize cell delay, cell area, and M2 usage. To improve the routing resource utilization, we propose an implicitly adjustable grid map, making the maze routing able to explore more routing solutions. The experimental results show that block placement using the DDA-aware cell library requires fewer filler cells than that using the traditional cell library by 25.1%, which achieves a block area reduction rate of 0.97%.

Multi-row cell structure has become popular for modern designs, especially for the multi-bit flip-flop (MBFF) cells, but has not been under full investigation in previous cell library synthesis researches. In this work, we propose an entire placement and routing flow for synthesizing multi-row cell layouts. The proposed new A*-based multi-row transistor placement algorithm can optimize the intra-row and inter-row connections. We also present the first MAX-SAT based detailed router to optimize the cross-row connections that also conform to primitive design rules, but not only to obtain a legal routing result in previous SAT-based detailed router. Experimental results show that the quality of synthesized cells is similar to that of a state-of-the-art cell library in [6], and better aspect ratios of multi-row cells also offer more flexible capability in assembling block designs under some aspect ratio constraints as compared to single-row cell library.

For 7nm technology node, cell placement with drain-to-drain abutment (DDA) requires additional filler cells, increasing placement area. This is the first work to fully automatically synthesize a DDA-aware cell library with optimized number of drains on cell boundary based on ASAP 7nm PDK. We propose a DDA-aware dynamic programming based transistor placement. Previous works ignore the use of M0 layer in cell routing. We firstly propose an ILP-based M0 routing planning. With M0 routing, the congestion of M1 routing can be reduced and the pin accessibility can be improved due to the diminished use of M2 routing. To improve the routing resource utilization, we propose an implicitly adjustable grid map, making the maze routing able to explore more routing solutions. Experimental results show that block placement using the DDA-aware cell library requires less filler cells than that using traditional cell library by 70.9%, which achieves a block area reduction rate of 5.7%.

In this paper, simple and compact Negative Bias Temperature Instability (NBTI) model is proposed. The model is based on the reaction-diffusion (tn) and hole-trapping (log(t)) theories. A single shot of DC stress and recovery data is utilized to express duty cycle dependence of NBTI degradation and recovery. Parameter fitting is proceeded by considering that the amount of recovery cannot be larger than stress degradation. The proposed model successfully replicates stress and recovery with various duty cycles.

With ever growing demands of mobile devices, low power consumption has become essential for VLSI circuits. Since standard cell libraries are typically used in many parts of VLSI circuits, their performance has a strong impact on realizing high speed and low power VLSI circuits. One of the most promising approaches for reducing the power consumption of the circuit is lowering the supply voltage. However this causes an increase of imbalance between rise and fall delays especially for cells having transistor stacks. For mitigating this imbalance, this paper proposes a structure of standard cells where the P/N ratio of each cell can be independently customized for near-threshold operation in VLSI circuits. The structure cancels the imbalance between rise and fall delays at the expense of cell area. The experiments with ISCAS'85 benchmark circuits demonstrate that the standard cell library consisting of the proposed cells reduces the power consumption of the benchmark circuits by 16% on average without increasing the circuit area, compared to that of the same circuit synthesized with a library which is not optimized for the near-threshold operation.

With the deep submicron technologies, IR drop and electromigration have become remarkable by decreasing of the power supply voltage. Therefore, power grid optimization becomes important to achieve the stable operation of large scale integration (LSI). However, it requires large computation time. In this paper, we propose a novel power grid simulation technique which can be applied to a large scale power grid. The proposal technique achieves ldquohigh speed processing by hardware acceleratorrdquo and ldquorealization of high accuracy computation with fixed point arithmeticrdquo. The proposed power grid simulation algorithm achieves 32 times more high speed processing than software processing. The accuracy is proven by experimental comparison with SPICE simulation.