A simple model is presented for estimating the delay of a multi-level combinational logic description prior to a technology-dependent mapping phase. The model proposes that delay through a node varies logarithmically with both the complexity and the fanout of the node's logic equation. This is a consequence of the observation that in high performance circuits, both the fan-in and fan-out of cells are bounded by small numbers. Model parameters are derived for three different CMOS ASIC (application specific integrated circuit) libraries, and the authors show how the predicted delays compare with the actual delays for three different industrial designs in each library. This model can serve as a proxy for delay during technology-independent logic optimization, much as literal counts serve as proxies for area.>

We have developed the concept of an abstract timing verifier that accepts plug-compatible timing models in a common framework containing the scheduling algorithms and the user interface. Depending on the design phase and the particular level of design representation used, the most suitable timing model can be plugged into this framework and operated in a standard way.