The design of active array structures in analog circuits requires careful matching to minimize the impact of variations. This work presents a constructive approach for building these arrays to directly incorporate shifts due to process variations, considering systematic first-order and second order gradients; to account for systematic layout effects, including parasitic mismatch and layout-dependent effects due to stress; and to ensure that the resulting layout delivers high performance. The proposed algorithms are targeted to FinFET technologies and are validated for multiple analog blocks in a commercial 12nm FinFET process. The layouts generated by the proposed method are demonstrated to provide better matching and performance than prior methods.

This article proposes a specification mining framework,FlowMiner, that automatically mines patterns from highly concurrent communication traces for system-on-chip (SoC) designs. It addresses the problem of the lack of comprehensive, accurate, and up-to-date specifications necessary to perform rigorous and thorough validation of complex SoC designs. The extracted patterns characterize how components of an SoC design communicate and coordinate with each other to realize various system functions. InFlowMiner, a set of inference rules and optimization techniques are presented to reduce mining complexity. Evaluation of this framework in several experiments shows promising results.

Common-centroid (CC) layouts are widely used in analog design to make circuits resilient to variations by matching device characteristics. However, CC layout may involve increased routing complexity and higher parasitics than other alternative layout schemes. This paper critically analyzes the fundamental assumptions behind the use of common-centroid layouts, incorporating considerations related to systematic and random variations as well as the performance impact of common-centroid layout. Based on this study, conclusions are drawn on when CC layout styles can reduce variation, improve performance (even if they do not reduce variation), and when non-CC layouts are preferable.

The common-centroid (CC) layout style is widely used to minimize the impact of variations among matched devices in analog blocks such as current mirror banks and differential pairs. This paper presents a constructive, performance-aware CC placement and routing algorithm for transistor arrays. Specifically, the proposed approach maximizes diffusion sharing, incorporates length of diffusion (LOD) based stress-induced performance variations, and mitigates resistive parasitics and electromigration (EM) hotspots, all of which are critical in modern technology nodes. The proposed algorithms are validated using cell- and circuit-level test cases in a commercial 12nm FinFET process. As compared to existing works, the cells generated using the proposed approach are shown to provide better performance in the presence of systematic variations, LOD, layout parasitics, and EM-induced degradation.

Concise and abstract models of system-level behaviors are invaluable in design analysis, testing, and validation. In this paper, we consider the problem of inferring models from communication traces of system-on-chip (SoC) designs. The traces capture communications among different blocks of a system design in terms of messages exchanged. The extracted models characterize the system-level communication protocols governing how blocks exchange messages, and coordinate with each other to realize various system functions. In this paper, the above problem is formulated as a constraint satisfaction problem, which is then fed to a satisfiability modulo theories (SMT) solver. The solutions returned by the SMT solver are used to extract the models that accept the input traces. In the experiments, we demonstrate the proposed approach with traces collected from a transaction-level simulation model of a multicore SoC design and a trace of a more detailed multicore SoC modeled in GEM5.

The quality of layouts generated by automated analog design have traditionally not been able to match those from human designers over a wide range of analog designs. The ALIGN (Analog Layout, Intelligently Generated from Netlists) project [2, 3, 6] aims to build an open-source analog layout engine [1] that overcomes these challenges, using a variety of approaches. An important part of the toolbox is the use of machine learning (ML) methods, combined with traditional methods, and this talk overviews our efforts. The input to ALIGN is a SPICE-like netlist and a set of perfor- mance specifications, and the output is a GDSII layout. ALIGN automatically recognizes hierarchies in the input netlist. To detect variations of known blocks in the netlist, approximate subgraph iso- morphism methods based on graph convolutional networks can be used [5]. Repeated structures in a netlist are typically constrained by layout requirements related to symmetry or matching. In [7], we use a mix of graph methods and ML to detect symmetric and array structures, including the use of neural network based approximate matching through the use of the notion of graph edit distances. Once the circuit is annotated, ALIGN generates the layout, going from the lowest level cells to higher levels of the netlist hierarchy. Based on an abstraction of the process design rules, ALIGN builds parameterized cell layouts for each structure, accounting for the need for common centroid layouts where necessary [11]. These cells then undergo placement and routing that honors the geomet- ric constraints (symmetry, common-centroid). The chief parameter that changes during layout is the set of interconnect RC parasitics: excessively large RCs could result in an inability to meet perfor- mance. These values can be controlled by reducing the distance between blocks, or, in the case of R, by using larger effective wire widths (using multiple parallel connections in FinFET technologies where wire widths are quantized) to reduce the effective resistance. ALIGN has developed several approaches based on ML for this purpose [4, 8, 9] that rapidly predict whether a layout will meet the performance constraints that are imposed at the circuit level, and these can be deployed together with conventional algorithmic methods [10] to rapidly prune out infeasible layouts. This presentation overviews our experience in the use of ML- based methods in conjunction with conventional algorithmic ap- proaches for analog design. We will show (a) results from our efforts so far, (b) appropriate methods for mixing ML methods with tra- ditional algorithmic techniques for solving the larger problem of analog layout, (c) limitations of ML methods, and (d) techniques for overcoming these limitations to deliver workable solutions for analog layout automation.

Automating analog layout is a long-standing research problem, with a history that goes back several decades. While digital design is largely automated today, analog layout has been significantly more resistant: automation has not made much headway in industry settings. There are several reasons for this, including:

The problem of analog design automation has vexed several generations of researchers in electronic design automation. At its core, the difficulty of the problem is related to the fact that machinegenerated designs have been unable to match the quality of the human designer. The human designer typically recognizes blocks from a netlist and draws upon her/his experience to translate these blocks into a circuit that is laid out in silicon. The ability to annotate blocks in a schematic or netlist-level description of a circuit is key to this entire process, but it is a process fraught with complexity due to the large number of variants of each circuit type. For example, the number of topologies of operational transconductance amplifiers (OTAs) easily numbers in the hundreds. A designer manages this complexity by dividing this large set of variants into classes (e.g., OTAs may be telescopic, folded cascode, etc.). Even so, the number of minor variations within each class is large. Early approaches to analog design automation attempted to use rule-based methods to capture these variations, but this database of rules required tender care: each new variant might require a new rule. As machine learning (ML) based alternatives have become more viable, alternative forms of solving this problem have begun to be explored.

Growing circuit complexity and design uncertainty has made it difficult to predict whether large circuits meet target property specifications. To address this, we conservatively approximate the failure probability estimate by defining an interval that bounds this probability. Doing so using an arbitrary sampling distribution requires a learner. Given that the learner's knowledge is imperfect, the interval must first capture its uncertainty. An ensemble of such learners can then be used to compensate for the bias. Lastly, we develop an adaptive sampling scheme to tighten the obtained interval with increased simulation resources, thus controlling the accuracy vs. turn-around-time trade-off.

Diagnosing out-of-specification failures in mixed-signal circuits has become increasingly challenging due to: (1) failures caused by interactions between input-signal conditions and design uncertainties, and (2) the need to identify critical input and uncertainty conditions that cause these regions. We propose a simulation-driven approach that first uses ensemble learning to extract if -- then rules that naturally solve both problems. By ranking, pruning and clustering these rules, we then construct non-linear failure regions which can be directly employed for pre-silicon debug, as demonstrated on a phase-locked loop circuit. Furthermore, these regions can be used to guide test pattern generation and/or assist with post-silicon debug.

Stability analysis is one of the key challenges in analog circuit design. As feature sizes continue to shrink and the effect of parasitics becomes more dominant, we are forced to deal with stability analysis of increasingly complex multiloop structures with potentially hundreds of loops-a task that can no longer be dealt with using traditional methods. An automated stability checker tool that detects sources of potential ringing behavior within a reasonable turnaround time has thus been made necessary. Such a tool would not just help in debug but could also serve as a postlayout validation tool. We thus present an efficient loop finder algorithm to identify sources of ringing in large linear analog circuits. At the heart of our automated stability checker are two newly developed computationally efficient algorithms-the first to detect all poles within a given region of interest with a high degree of confidence and the second to extract second-order approximations of node impedance transfer functions given these pole locations. In this paper, we discuss these algorithms in detail, propose various optimization heuristics to further speed up the pole discovery algorithm, and then go on to develop a parallel implementation of both these underlying algorithms. It is demonstrated that these approaches together allow us to outperform the original loop finder algorithm based on direct eigen methods by two to four orders of magnitude and thus enable stability analysis of even larger extracted industrial designs than was previously possible while providing reasonable turnaround time.

Stability analysis is one of the key challenges in the design of large linear analog circuits with complex multi-loop structures. In this paper, we present an efficient loop finder algorithm to identify potentially unstable loops in such circuits. At the heart of our automated stability checker lie two newly developed computationally efficient algorithms --- the first to detect all poles within a given region of interest and the second to extract second order approximations of node impedance transfer functions given these pole locations. It is shown that the proposed technique outperforms existing stability methods by more than one order of magnitude for medium sized circuits and enables stability analysis of large extracted industrial designs which was previously infeasible.