An approximate block elimination (ABE) method for constructing preconditioning matrices in the block iteration of systems of linear equations is presented. Four families of preconditioning matrices based on this approach are identified for solving the 2*2 block equations with the Jacobian resulted from the 3-D one-carrier semiconductor device analysis problem. The fully coupled Newton's method is used as a test case on a parallel computer, the Intel iPSC/2 hypercube. There are ten different preconditioning transformations including the alternate block factorization (ABF) and the modified singular perturbation (MSP) schemes. The results from computational experiments indicate that eight of these preconditioning matrices significantly extend the convergence region of the block Gauss-Seidel iteration process of Newton steps and five of them speed up the convergence with a factor of up to more than an order of magnitude.>

A 3-D device solver (STRIDE), capable of solving grids up to 250,000 nodes, has been developed on a message passing multiprocessor. By the use of iterative matrix solvers and Gummel style nonlinear iteration schemes, user memory per node is reduced over use of direct solvers and Newton schemes. By using an independent-edge-grouping scheme to increase the vector length to the order of the number of variables, the vector processing efficiency is significantly increased without additional floating point operations. The modified-singular-perturbation (MSP) scheme is extended to two-carrier simulations. This significantly speeds up the convergence rate of Gummel style nonlinear iterations. Physical insight gained from the MSP schemes also leads to an automatic switching scheme between various nonlinear schemes based on the monitoring of certain matrix parameters. Application of STRIDE is demonstrated by an analysis of latchup trigger current dependence on layout arrangement.>

A 3-D one-carrier device solver has been developed on an Intel iPSC2 hypercube multiprocessor which can handle over 130 K nodes. CPU time averages 20 min per bias point on a 50 K-node MOSFET example. Slotboom variables are used in conjunction with the Scharfetter-Gummel current discretization scheme. A scaling scheme is proposed which produces n, p variables from the Slotboom variables. An improved damped-Newton scheme, which maintains the iteration numbers at below fifteen for high gate biases, is used in solving Poisson's equation. The performance of a previously proposed initial guess scheme is improved through the use of a novel update strategy during the Poisson solution stage after the initial guess step. This improvement allows stable calculation for voltage steps as high as 5 V. A modified singular perturbation scheme (MSP) has been proposed whose implementation speeds up the convergence under high-V/sub gs/ and -V/sub ds/ bias conditions by a factor of three to six. A block matrix analysis of the MSP scheme yields insight into its performance.>