This article proposes a reliable and secured polar coding for the network-oriented cloud control system (NOCCS) in the context of security, reliability, and scalability. A low-complexity variant of the 3-D chaos system is proposed to accomplish internal chaos-encryption-based polar coding for orthogonal frequency division multiplexing over an active power network (OFDM-AON) to ensure the reliability and security of the NOCCS. Internal encryption is achieved by disrupting the correlation of the information bits index and frozen bits index along with the subcarrier by the three chaotic behavioral sequences obtained by Chua's system while encoding polar code. The method is tested on the fiber optic channel between the cloud computing and a local controller placed at a significant distance, thoroughly connected through the fiber optic cable network, and utilizing a 16 quadrature amplitude modulation-OFDM (QAM-OFDM) signal transmission. Our experimental results and performance analysis demonstrate that the proposed encryption scheme produces a 2.5-dB gain in sensitivity on the local controller end at a bit error rate (BER) of 10$^{-3}$compared to the conventional QAM-OFDM. Furthermore, the spacing window for the key distribution is 10$^{75}$, which can be regarded as a protection degree against any brute-force attack from unauthorized optical network units that act as local controllers. Considering the BER enhancement, reliability, and security, the proposed QAM-OFDM-based chaos encryption polar encoding can be ranked as a suitable choice for the NOCCSs data transmission and protection against any brute-force or differential attacks.

The concept of Low Density Parity Check (LDPC) coding over Galois Fields GF (q = 2p) is a generalization of the industry standard binary LDPC coding. The performance for short block length codes is significantly higher for non-binary codes (over higher order GF fields), but on the other hand, the decoding complexity is increased. Therefore the hardware implementation of a decoder is still a challenging task. Most of the few implementations known from the literature use multiplierless computing units. In this article we present a different approach that does not exclude multiplier blocks from the decoder module. This approach is specifically intended for FPGA (Field Programmable Gate Array) implementation. We propose the decoding algorithm formulation that uses multiplications in the computation step of the Check Nodes and summations performed in the Bit Nodes. The main reason is to enable mapping a part of the algorithm to the multiplier cores available in the FPGA devices. In the article we present the decoder structure that has been developed and the construction of its building blocks. We also provide synthesis results for the Xilinx FPGAs and simulation results for a simple BPSK (Binary Phase Shift Keying) modulation model over AWGN (Additive White Gaussian Noise) channel.

Much attention has been paid recently to the so-called layered decoding of LDPC codes, also known as turbo-decoding message passing (TDMP). The TDMP algorithm for decoding LDPC codes is known to possess some desirable features, such as fast convergence speed, reduced memory requirements and reduced implementation complexity in comparison with standard two-phase message passing algorithm. In this paper we analyze an important issue connected with hardware implementation of TDMP algorithm, namely the finite precision representation of messages influence on the decoding performance. Constrained dynamic range of the finite precision representation of messages entails overflow errors. We present an analysis revealing that in the subsequent decoding iterations, the subtraction of non-overflowed intrinsic message from overflowed extrinsic message is a source of errors that have substantial impact on the decoding results. The analysis is confirmed by simulation results showing significant performance loss. However this performance loss can be almost completely eliminated with a basic modifications in the messages computation algorithm. Effectiveness of the presented modifications is confirmed by simulation results obtained with hardware TDMP decoder implementation that has been developed.