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Eugene Z. Xia

dblp:69/118 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1992
—ORCID · unresolved

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 77% Performance modeling and evaluation · 12% High-performance computing · 12%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
circuit simulation		 0.011992
Parallel waveform-Newton algorithms for circuit simulation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1992
Electronic design automation › circuit simulation
parallel circuit simulation		 0.011992
Parallel waveform-Newton algorithms for circuit simulation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1992
High-performance computing
parallel numerical algorithms		 0.011992
Parallel waveform-Newton algorithms for circuit simulation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1992
Performance modeling and evaluation › simulation › architectural simulation
simulation acceleration		 0.011992
Parallel waveform-Newton algorithms for circuit simulation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1992

Methods — techniques the papers use, named apart from their topics

waveform relaxation · 0.0newton method · 0.0multigrain parallelization · 0.0
YearPublicationVenuePosition
1992 Parallel waveform-Newton algorithms for circuit simulation
abstract
The parallelization of the waveform-relaxation-Newton (WRN) method for circuit simulation is described. The techniques are applied at three levels of granularity: subcircuits are processed in parallel for large-grain parallelism, time points are processed in parallel for medium-grain parallelism, and devices are processed in parallel for fine-grain parallelism. The effectiveness of each of these approaches is demonstrated with the PSPLAX program (which is a parallel version of a WRN program called SPLAX) using a number of industrial examples. Currently, PSPLAX is implemented on an Alliant FX/80 with eight processors. The results indicate that the combination of these approaches should be effective on larger systems.>
Eugene Z. Xia, Res Saleh
 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1