As transistors continue to shrink so does their operating voltage. While this reduction is beneficial in many aspects, in a complex integrated circuit (IC) it adds more power domains to the system. Traditionally, this challenge is addressed through the use of voltage converters, which, however, introduce drawbacks, including increased on-chip or off-chip area, additional power consumption, and reduced reliability. Circuit stacking has been proposed as an alternative approach, in which circuits are placed in series such that the ground of a circuit serves as the supply of the next circuit. This scales the supply voltage by the number of circuits in the stack, effectively reducing the number of voltage converters needed. Unfortunately, mismatches in current draw among stacked circuits can cause significant deviations in voltage ranges, inducing timing violations for synchronous circuits. Multi-Threshold NULL Convention Logic (MTNCL) is an asynchronous paradigm that is resilient to timing and voltage variations. This paper presents silicon experiments of stacked MTNCL circuit architecture in comparison with its simulated counterparts.

Multi-Threshold NULL Convention Logic (MTNCL) is an ultra-low-power asynchronous design methodology that eliminates global clock distribution using local handshaking and completion detection. However, conventional MTNCL suffers from limited performance due to static gate structures and explicit NULL-wave generation. This paper presents Domino MTNCL, a high-performance dynamic-style MTNCL approach that reuses existing locally generated handshaking signals for phase control. Post-layout evaluations demonstrate that the proposed approach achieves higher throughput, reduced propagation delay, lower active energy and leakage power, and reduced design area relative to conventional MTNCL implementations.

The problem of prescribed performance control (PPC) for the multi-input multi-output block-triangular nonlinear systems under output constraints is investigated in this article. It is focused on the scenario where the references are not known in advance. This renders the related solutions infeasible and becomes more challenging under the totally unknown and inherently nonlinear dynamics of the system. To overcome this challenge, a novel robust decoupling PPC strategy is developed in this article, in which an online boundary generation scheme and a smoothly constraint switching rule are devised and introduced. The resulting controller ensures that the system outputs evolve within their respective constraint bands and track the references with the predetermined overshoot, settling time and accuracy. Moreover, it is independent of function approximation, parameter identification, or disturbance estimation, despite the unbounded nonlinearities, unmatched disturbances and unknown dynamics. A comparative experiment on a 2-DOF serial flexible link robot is conducted to show the efficacy and superiority of our low-complexity high-performance control approach.

Volatile memories, like registers and SRAM, are integral parts of any CPU or system-on-chip (SoC). They store a variety of on-chip sensitive assets, such as cryptographic keys, intermediate cipher computations, passwords, obfuscation keys, and hardware security primitive outputs. Although such data should be erased as soon as the power is off, it can be susceptible to cold boot attacks. Cold boot attack is based on remanence effect of memories, which says that memory contents do not disappear immediately after power is cut; they fade gradually over time, which can be significantly prolonged at low temperatures. This effect can be exploited by rebooting a running machine and reading what is left in memory. This paper proposes a self-destructive latch extending to amnesiac register, protecting sensitive data when temperature goes to freezing conditions. Our proposed latch senses the temperature drop required during such attacks and reacts instantaneously by entering a forbidden data state, erasing registers stored data. The design uses a NULL convention logic (NCL)-based polymorphic NOR/NAND gate, which changes its functionality with temperature. Our results show that latch and register are stable across process variation, corresponding to attack with 99% and 80% confidence. Even for the 20% where data is not destroyed, in 9.5% of cases data flips its state, making reliable extraction difficult for an attacker. The polymorphic mechanism is straightforward to implement due to its easy implementation, and temperature threshold for self-destructive behavior is easily programmed using only one gate voltage.

As smart home IoT systems gain popularity, they inevitably become targets for security risks and concerns. Among various cyber-attacks targeting these systems, the fake event attack poses significant issues due to its ability to manipulate secure devices through automation rules. In response to this threat, we propose TrustEvent - a system designed to offer end-to-end event signature verification. By integrating TrustEvent with existing home automation platforms, event authenticity is verified against signatures generated from edge devices before these events trigger automation rule execution. Notably, we have developed a signature proxy module, enhancing our system's compatibility across various platform scenarios. We have implemented a TrustEvent prototype in conjunction with existing commercial smart home IoT platforms, evaluating its overhead in the process. Our experimentation demonstrates that our system only marginally increases the automation execution latency, by an average of 3.74 seconds, representing a acceptable compromise for enhanced security.

Along with the increasing popularity of smart home IoT devices, more users are turning to smart home automation platforms to control and automate their IoT devices. However, IoT automation is vulnerable to spoofed event attacks. Given that IoT devices are intricately linked with the physical environment and operate autonomously, event-based attacks can pose serious safety and security challenges. Our observations show that many IoT events are accompanied by visual modifications in objects such as shape alterations (for example, contact sensor events correspond with door movement) or changes in color/brightness (for example, a functioning microwave oven with the internal light switched on). These alterations can be detected by the commonly deployed smart cameras, providing a visually rich but challenging to manipulate channel for verifying IoT events. We introduce IoTSentry, the first system of its kind to extract high-level semantic information from streaming video data and pixels for IoT event verification. We have designed a Siamese deep neural network to identify variations in the appearance of IoT devices and interior objects. These are used as the yardstick for verifying IoT events received at IoT automation platforms. Upon assessing IoTSentry with 21 IoT devices (8 types), the results demonstrate that IoTSentry can be trained within 120 seconds, yielding an accuracy rate of over 96.7% in recognizing device states. We have deployed the 21 IoT devices and IoTSentry on two real-world smart home test sites. Over the course of our one-week evaluation, IoTSentry consistently achieved an average detection rate of 99.24% in identifying attack instances. Moreover, it triggered no more than 2 false alarms per day on each test site.

Calculating the number of distinct values (i.e., NDV) in a column of a big table is costly yet fundamental to a variety of database applications such as data compression and profiling. To reduce the high time and space cost, a number of sketch methods (e.g., HyperLogLog) have been proposed, which estimate the NDV from a constructed compact data summary of distinct values. However, these methods fail or are costly to manage fully-dynamic scenarios where data is often inserted into and deleted from the table. To solve this issue, we propose a novel sketch method,Half-Xor. Our Half-Xor sketch consists of a compact bit matrix and a small counter array, and it needs to set a few bits and update a counter when handling a data insertion/deletion. Compared with the state-of-the-art mergeable method, our experimental results demonstrate that our method Half-Xor is up to 6.6 times more accurate under the same memory usage and reduces the memory usage by up to 16 times to achieve the same estimation accuracy.

Given a set S, Membership Querying (MQ) answers whether a query element $q\in S$. It is a fundamental task in areas like database systems and computer networks. In this paper, we consider a more general problem, Multi-Set Multi-Membership Querying (MS-MMQ). Given n sets $S_0,łdots,S_n-1 $, MS-MMQ answers which sets contain element q. A direct way to address MS-MMQ is to build an MQ structure (e.g., Bloom Filter) for each set. However, the query and space complexities grow linearly with n and become prohibitive for a large n. To address this challenge, we propose a novel Circular Shift and Coalesce (CSC) framework to efficiently achieve approximate MS-MMQ. Instead of building an MQ data structure for each set, the CSC index encodes all n sets into a compact sketch and retrieves only a few bytes in the sketch for a query, which achieves high memory-efficiency and boosts the query speed by several times. CSC is compatible with mainstream data structures for Approximate MQ. We conduct experiments on real-world datasets and results demonstrate that our framework is up to 91.2 times faster and up to 48.9 times more accurate than state-of-the-art methods.

Physical unclonable functions (PUFs) are widely researched security primitive in the digital and analog domain but have yet to be explored for asynchronous circuits. In this paper, we propose novel optimization methods to design a weak Asynchronous RESet (ARES) PUF that exploits random start-up characteristics of Threshold M of N Null Conventional Logic (NCL) gates as a source of entropy. We employ two different methods to design the ARES PUF. The first includes traditional delay matching techniques using linear programming-based optimization, whereas the second one uses the genetic algorithm (GA) with delay matching as a fitness function. Both methodologies are explained with analysis and design specifications required to model NCL TH22 gates to achieve PUF characteristics. Threshold 2 of 2 (TH22) and 4 of 4 (TH44) gates are used as test cases for evaluation and comparison. Simulation results using initial delay matching techniques at 90nm and 65nm technology in HSPICE shows that the proposed ARES PUF has a uniqueness of 49.98% and reliability of 96.53% across VDD variation (±10%) and 93.39% across temperature variation (0°C-80°C). Whereas, the GA method can optimize NCL cells to form a PUF with 49% uniqueness at 65nm with an average reliability of 96.4% across VDD and 93.82% across temperature. Preliminary silicon results for proposed TH22 at TSMC 90nm technology node shows a 34% improvement in uniqueness compared to standard TH22 gate with best-case uniqueness of 53.3% and reliability of 100% respectively across repeated measurements (noise). Unlike standard TH22, standard TH44 performs better with 47.62% best-case uniqueness and 98.1% reliability1.

While a number of methods exist for asynchronous circuit synthesis, there are limited applicable test methodologies. This paper presents a Built-In Self-Test (BIST) method for Multi-Threshold NULL Convention Logic (MTNCL) asynchronous circuits, which utilizes standard synchronous tools, and is automated to achieve maximum fault coverage while minimizing area overhead and test time.

Outsourcing data to a third-party cloud provider has become quite common with the increasing use of cloud computing. This brings convenience, as well as the concern for data security and privacy. It is believed that data encryption alone is often not enough to protect users' privacy from the cloud provider. According to previous work, the sequence of storage locations accessed by the client can leak up to 90% of the sensitive information, even with data encrypted. In this context, Oblivious RAM (ORAM) is proposed. ORAM algorithms allow the client to hide its access pattern from the service provider while introducing a lot of extra operations. Among all the prototypes, Path ORAM is one of the most promising designs. However, there are still redundant memory accesses that can be removed without harming the security of traditional ORAM as we observed. We came up with three optimization techniques, including path merging, ORAM request scheduling, and merging aware caching. We also propose a prefetching technique to further decreasing the access overhead. Moreover, we also illustrate the compatibility of Fork Path and some state-of-the-art Path ORAM optimizations. Compared to traditional Path ORAM approaches, our Fork Path ORAM can reduce overall performance overhead and power consumption of memory system by 65% and 44%, while the design overhead is trivial.

Asynchronous logic offers the advantages of no clock tree, robust circuit operation, avoidance of worst-case timing margins, and a reduced emission spectrum. Thus, computational paradigms are sought to attain advantages of clockless logic by leveraging the complementary characteristics of emerging devices and CMOS transistors within novel circuit designs. This paper introduces Spin Torque Enabled NULL Convention Logic (STENCL), which exploits the physical characteristics of non-volatile Domain-Wall (DW) and memristive devices to realize the Quasi-Delay-Insensitive (QDI) NULL Convention Logic (NCL) asynchronous design methodology. First, a formal algorithm is developed to transform NCL-based threshold m-of-n gate realizations to STENCL, in order to generate the corresponding input memristance and NULL module memristance required for nominal currents achieving DW device biasing. Second, hysteresis and set/reset conditions are realized by determining the corresponding current fluctuations required to move the DW within each threshold logic gate to realize all 27 foundational NCL gate structures, which are then simulated to assess energy and delay metrics. Third, a case study of a four-stage pipelined 32-bit IEEE single-precision floating point co-processor implemented as a dual-rail STENCL architecture is compared to a conventional CMOS-based NCL design implemented by an IBM SOI1250 45nm CMOS process. Fourth, a sensitivity analysis is performed to assess the impact of write accuracy and drift on memristor and DW device operation. Results indicate that STENCL-based designs achieve between 2-fold to 20-fold reduction in energy consumption with up to 8-fold reduction in area, over an equivalent CMOS-based NCL design for 32-bit full adders. Comparisons for various four-stage pipelined 32-bit IEEE single-precision floating-point co-processors and ISCAS benchmarks further substantiate those benefits for operation within acceptable tolerances at identical process technology nodes.

Printed circuit boards (PCBs) are a basic necessity for all modern electronic systems but are becoming increasingly vulnerable to cloning, overproduction, tampering, and unauthorized operation. Most efforts to prevent such attacks have only focused on the chip level, leaving a void for PCBs and higher levels of abstraction. In this article, we propose the first ever obfuscation-based framework for the protection of PCBs. Central to our approach is a permutation block that hides the inter-chip connections between chips on the PCB and is controlled by a key. If the correct key is applied, then the correct connections between chips are made. Otherwise, the connections are incorrectly permuted, and the PCB/system fails to operate. We propose a permutation network added to the PCB based on a Benes network that can easily be implemented in a complex programmable logic device or field-programmable gate arrays. Based on this implementation, we analyze the security of our approach with respect to (i) brute-force attempts to reverse engineer the PCB, (ii) brute-force attempts at guessing the correct key, and (iii) physical and logistic attacks by a range of adversaries. Performance evaluation results on 12 reference designs show that brute force generally requires prohibitive time to break the obfuscation. We also provide detailed requirements for countermeasures that prevent reverse engineering, unauthorized operation, and so on, for different classes of attackers.

Physical Unclonable Functions (PUFs) have been widely proposed as security primitives to provide device identification and authentication. Recently, PUFs based on Non-volatile Memory (NVM) are widely proposed since the promise of NVMs' wide application. In addition, NVM-based PUFs are considered to be more immune to invasive attack and simulation attack than CMOS-based PUFs. However, the existing NVM-based PUF either shows the unreliability under environmental variations or need extra modifications to the IC manufacturing process. In this work, we propose err-PUF, a novel PUF design based on the cell error rate distribution of STT-RAM. Instead of using the distribution directly, we generate a stable fingerprint based on a novel concept called Error-rate Differential Pair (EDP) without modifications to the read/write circuits. Comprehensive results demonstrate that err-PUF can achieve sufficient reliability under environmental variations, which can significantly impact the cell error rates. Moreover, compared with existing approaches, err-PUF has a higher speed and lower power consumption with negligible overhead.

The rapid growth of Internet-of-things and other electronic devices make a huge impact on how and where data travel. The confidential data (e.g., personal data, financial information) that travel through unreliable channels can be exposed to attackers. In hardware, the confidential data such as secret cipher keys are facing the same issue. This problem is even more serious when the IP is from a 3rd party and contains scan-chains. Thus, data flow tracking is important to analyze possible leakage channels in fighting against such hardware security threats. This paper introduces a method for tracking data flow and detecting potential hardware Trojans in gate-level soft IPs using assets and Structural Checking tool.

As more sensitive data are shared, transmitted, and stored on electronic devices, data security has become an important concern. Encryption algorithms that are safe against software-based attacks still face security threats from side channel attacks. For example, an encryption device's power consumption or operational timing can be correlated to the data being processed by the device, which can give away the device's secret key. Dual-spacer Dual-rail Delay-insensitive Logic (D3L) is an IC design methodology that has been proved effective in mitigating power and timing attacks; however, large energy and area overheads of D3L circuits have hindered their applicability. In this paper an IC design methodology named Multi-Threshold D3L (MTD3L) is presented that achieves all D3L security advantages with considerably reduced overhead.

Prior work has shown that printed circuit board (PCB) reverse engineering can be accomplished with inexpensive home solutions as well as state-of-the-art technologies. Once the information of how components on a PCB are connected is determined, an adversary can steal the IP, clone the design, determine points of attack on a system, etc. Existing chip-level obfuscation techniques are not applicable to board level due to the significant differences between chips and PCBs. In this paper, we propose a PCB obfuscation approach that relies on permutation blocks to hide the interconnects among the PCB's circuit components. A detailed framework is provided to implement the proposed approach and evaluate its performance. Potential attacks and countermeasures are also discussed. Results obtained from five industrial reference designs show that it is nearly impossible to break the proposed approach by brute force, even under pessimistic assumptions. Our investigation also reveals that PCBs containing a programmable component with 64 pins (or more) are well-protected by our approach, making it suitable for a large percentage of systems and applications.

Oblivious RAM (ORAM) is a cryptographic primitive that can prevent information leakage in the access trace to untrusted external memory. It has become an important component in modern secure processors. However, the major obstacle of adopting an ORAM design is the significantly induced overhead in memory accesses. Recently, Path ORAM has attracted attentions from researchers because of its simplicity in algorithms and efficiency in reducing memory access overhead. However, we observe that there exist a lot of redundant memory accesses during the process of ORAM requests. Moreover, we further argue that these redundant memory accesses can be removed without harming security of ORAM. Based on this observation, we propose a novel Fork Path ORAM scheme. By leveraging three optimization techniques, namely, path merging, ORAM request scheduling, and merging-aware caching, Fork Path ORAM can efficiently remove these redundant memory accesses. Based on this scheme, a detailed ORAM controller architecture is proposed and comprehensive experiments are performed. Compared to traditional Path ORAM approaches, our Fork Path ORAM can reduce overall performance overhead and power consumption of memory system by 58% and 38%, respectively, with negligible design overhead.

Emerging non-volatile memories (NVMs) have been considered as promising alternatives of DRAM for future main memory design. The NVM main memory has advantages of low standby power, high density, and good scalability. Its non-volatility, however, induces a security design challenge that data retained in memory after power-off need to be protected from malicious attacks. Although several approaches have been proposed to solve this problem through data encryption, they have some limitations such as high design complexity and non-trivial timing/energy overhead. Moreover, these techniques decrease the lifetime of NVM main memory due to extra write operations caused by encryption. In order to overcome these limitations, we propose an efficient PAD-XOR based encryption scheme in this work. A novel PAD generator based on a randomizer and several sub-PAD tables is introduced. With the PAD generator, our encryption scheme can provide run-time data protection to all data in NVM memory with low timing and power overhead. In addition, the encryption process can co-operate with wear-leveling of NVM to reduce design complexity. More important, our encryption technique has no impact on lifetime because no extra writes are incurred. Experimental results demonstrate that, compared to prior approaches, our design can achieve the same security strength with substantial lower overhead in respect of timing, energy consumption, and design complexity.

Radio frequency identification (RFID) tags are low-cost devices that are used to uniquely identify the objects to which they are attached. Due to the low cost and small size that are driving the technology, a tag has limited computational capabilities and resources. These limitations constrain the use of conventional encryption algorithms and security protocols to prevent cloning and counterfeiting of an RFID tag. Therefore, we propose to create an electronic fingerprint of a tag based upon the physical attributes of the tag. We have fingerprinted RFID tags based upon their minimum power responses measured at multiple frequencies. The fingerprint can be used effectively to identify the tags in the future with high probability and to detect counterfeit tags. This mechanism does not increase the cost of the tag and can be applied to any existing tag, because it is independent of the computational capabilities and resources of the RFID tag.

In this paper, a novel design is proposed for eliminating glitches and signal bounces during wake-up events that result from incorporating multi-threshold CMOS (MTCMOS) into asynchronous NULL Convention Logic (NCL) circuits. A one-stage 8x8 NCL array multiplier is designed using the proposed method and compared with the previously published paradigm. Evaluation results of glitches, throughput, and power efficiency have shown advantages of the proposed design in all these categories over the state-of-the-art. The effect of supply voltage scaling on the proposed design is also examined and presented.

Power-awareness indicates the scalability of the system energy with changing conditions and quality requirements. Multipliers are essential elements used in DSP applications and computer architectures. Although Boolean multipliers have natural power awareness to the changing of input precision, deeply pipelined designs do not have this benefit. A 2-dimensional pipeline gating scheme is proposed in this paper to solve this problem and improve the power awareness in these designs. 2-Dimensional pipeline gating is to gate the clock to registers in both vertical direction (data flow direction in pipeline) and horizontal direction (within each pipeline stage). This technique only needs very little additional area and the overhead is hardly noticeable. A set of array multipliers were designed and tested. Results show that the new 16-bit array multiplier using this technique has an average power saving of 66% and an average latency reduction of 47% over original design under equal input precision probabilities.