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S. Murphy

dblp:69/1396 · DBLP profile ↗
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4ranked-venue papers
2as first author
0since 2021 · last 2011
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Theory of computation · 2 · 2 first-authorSecurity and privacy · 1Graphics, computer vision, multimedia, augmented reality and games · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Network and information security
2 papers
Cryptographic primitives and cryptanalysis · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Cryptographic primitives and cryptanalysis
block cipher cryptanalysis
0.222011
Overestimates for the Gain of Multiple Linear Approximations in Symmetric Cryptology · IEEE Trans. Inf. Theory 2011
The Independence of Linear Approximations in Symmetric Cryptanalysis · IEEE Trans. Inf. Theory 2006
Cryptographic primitives and cryptanalysis
linear cryptanalysis
0.222011
Overestimates for the Gain of Multiple Linear Approximations in Symmetric Cryptology · IEEE Trans. Inf. Theory 2011
The Independence of Linear Approximations in Symmetric Cryptanalysis · IEEE Trans. Inf. Theory 2006
Cryptographic primitives and cryptanalysis › linear cryptanalysis
multiple linear approximations
0.222011
Overestimates for the Gain of Multiple Linear Approximations in Symmetric Cryptology · IEEE Trans. Inf. Theory 2011
The Independence of Linear Approximations in Symmetric Cryptanalysis · IEEE Trans. Inf. Theory 2006

Methods — techniques the papers use, named apart from their topics

gain analysis · 0.1stochastic independence · 0.1covariance analysis · 0.1
YearPublicationVenuePosition
2011 Overestimates for the Gain of Multiple Linear Approximations in Symmetric Cryptology
abstract
This paper shows that Corollary 1 of “On Multiple Linear Approximations” is incorrect. In particular, the value given for the gain by Corollary 1 is likely to be a significant overestimate of this quantity. Thus, any data requirements for linear cryptanalysis with multiple linear approximations based on this value for the gain are highly questionable.
S. Murphy
IEEE Trans. Inf. Theory1
2007 Projective aspects of the AES inversion
Wen-Ai Jackson, S. Murphy
Des. Codes Cryptogr.2
2006 The Independence of Linear Approximations in Symmetric Cryptanalysis
abstract
A theoretical framework for the use of multiple linear approximations in the linear cryptanalysis of block ciphers is given. The covariance of two mask counts is derived, and it is shown that under appropriate conditions the mask counts in linear cryptanalysis are stochastically independent, whether or not the masks are linearly independent. Some consequences of these observations are also considered
S. Murphy
IEEE Trans. Inf. Theory1
2001 A programmable processor with 4096 processing units for media applications
abstract
Media data delivery and processing such as telecommunications, networking, video processing, speech recognition and 3D graphics is increasing in importance and will soon dominate the processing cycles consumed in computer-based systems. This paper describes a processor called Linedancer, that provides high media performance with low energy consumption by integrating associative SIMD parallel processing with embedded microprocessor technology. The major innovations in the Linedancer is the integration of thousands of processing units in a single chip that are capable to support software programmable high-performance mathematical functions as well as abstract data processing. In addition to 4096 processing units, Linedancer integrates on a single chip a RISC controller that is an implementation of the SPARC architecture, 128 kbytes of data memory, and I/O interfaces. The SIMD processing in Linedancer implements the ASProCore architecture, which is a proprietary implementation of SIMD processing, operates at 266 MHz with program instructions issued by the RISC controller. The device also integrates a 64-bit synchronous main memory interface operating at 133 MHz (double-data rate, DDR), and a 64-bit 66 MHz PCI interface.
Anargyros Krikelis, Ian P. Jalowiecki, David L. Bean, Ryan Bishop, M. Facey, D. Boughton, S. Murphy, M. Whitaker
ICASSP7