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K. Heron

dblp:69/1500 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1980
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware reliability and fault tolerance · 87% Processor architecture and microarchitecture · 13%

Topics — the 2 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware reliability and fault tolerance › error recovery
backward error recovery		 0.011980
A Recovery Cache for the PDP-11 · IEEE Trans. Computers 1980
Hardware reliability and fault tolerance › error recovery
recovery cache		 0.011980
A Recovery Cache for the PDP-11 · IEEE Trans. Computers 1980

Methods — techniques the papers use, named apart from their topics

hardware add-on design · 0.0
YearPublicationVenuePosition
1980 A Recovery Cache for the PDP-11
abstract
Backward error recovery is an integral part of the recovery block scheme that has been advanced as a method for providing tolerance against faults in software; the recovery cache has been proposed as a mechanism for providing this error recovery capability. This correspondence describes a recovery cache that has been built for the PDP-11 family of machines. This recovery cache has been designed to be an "add-on" unit which requires no hardware alterations to the host CPU but which intersects the bus between the CPU and the memory modules. Specially designed hardware enables concurrent operation of the recovery cache and the host system, and aims to minimize the overheads imposed on the host.
P. A. Lee, N. Ghani, K. Heron
 IEEE Trans. Computers3