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Michael R. Warpenburg

dblp:69/1878 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1982
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Processor architecture and microarchitecture · 77% Parallel and multicore computing · 23%
Computer graphics and multimedia
1 paper
Image and video processing · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Image and video processing
image resampling
0.011982
SIMD Image Resampling · IEEE Trans. Computers 1982
Processor architecture and microarchitecture
SIMD
0.011982
SIMD Image Resampling · IEEE Trans. Computers 1982
Parallel and multicore computing › parallel architecture
microprocessor array
0.011982
SIMD Image Resampling · IEEE Trans. Computers 1982

Methods — techniques the papers use, named apart from their topics

offset-based resampling theory · 0.0SIMD algorithms · 0.0SIMD algorithm · 0.0
YearPublicationVenuePosition
1982 SIMD Image Resampling
abstract
Due to advances in VLSI technology, large scale arrays of microprocessors forming parallel processing systems have become feasible. The use of such a microprocessor array operating in the SIMD (single instruction stream-multiple data stream) mode to perform image resampling is explored. A general theory of resampling in terms of offsets is developed. From this, an approach to performing resampling in an SIMD environment is given. Detailed analysis of the SIMD algorithm is presented, and computational speedup over conventional uniprocessor approaches is shown to be approximately a factor of N where N is the number of processors used.
Michael R. Warpenburg, Leah J. Siegel
IEEE Trans. Computers1