This paper presents design and analysis of a latch-based time amplifier (TA). While prior studies have primarily focused on TA gain and output characteristics, this work extends the analysis to include input-referred jitter, input dynamic range, latency, and gain behavior. Analytical equations are derived to facilitate comparisons with other TA architectures, offering insights into the performance trade-off of latch-based TA. The proposed models are validated through both simulations and measurements. A prototype latch-based TA is fabricated in a 28-nm CMOS LP process to demonstrate the effectiveness of the analysis.

This paper presents a time-interleaved analog-to-digital converter mismatch calibration, which can be adapted to any interleaving factor and calibrate offset, gain, time skew and bandwidth mismatches. Moreover, the proposed scheme utilizes a non-return-to-zero pilot signal, avoiding the high-resolution requirements of sinusoidal generators. In addition, there are no multiplications in the detection path in contrast with the state-of-the-art approaches. Consequently, the proposed calibration presents the smallest complexity in terms of hardware requirements compared to previous work (to the author’s knowledge). Therefore, the proposed calibration can be made with the smallest area and power consumption. Numerical simulations show an SNDR improvement of 49.52 dB for a 12-bit 4-channel TI-ADC and an SNDR improvement of 29.64 dB for an 8-bit 32-channel TI-ADC when random mismatches are applied. The measurement results show an SNDR improvement of 24.68 dB for a 3.6 GS/s 2-channel TI-ADC experimental board.

The time-interleaved analog-to-digital converter has shown to be a key component of the latest ultra-wide band systems. Unfortunately, the sub-analog-to-digital converters are prone to parameter deviations caused by process-voltage-temperature, which can affect the output linearity. This article presents a foreground time-interleaved analog-to-digital converter mismatch calibration, which is one of the few available in the literature that can be adapted to any interleaving factor and calibrate overall frequency-dependent mismatches. Moreover, the proposed scheme is highly suited to state-of-the-art transceivers without the need for extra analog expensive circuitry or input signal purity. The foreground signal and correction structure complexity are greatly alleviated due to the developed mismatch detection and genetic algorithm logic. Numerical simulations and measurement results are presented. A commercial 3.6-GS/s time-interleaved analog-to-digital converter was utilized to verify the algorithm performance and experimental issues regarding mixed mismatches are addressed.

A hybrid Miller-Cascode compensation (HMCC) scheme incorporating Miller compensation (MC) and cascode compensation on a nonsignal path (CCNSP) in the two-stage amplifiers is presented. The proposed HMCC resolves issues in other compensations such as CCNSP, cascode compensation on a signal path (CCSP), and hybrid cascode compensation (HCC) such that the gain peaking near unity gain frequency (UGF) in the open-loop transfer function is alleviated, which results in faster settling. To understand and validate the merit of the proposed HMCC, the locations of poles and a zero are analyzed through the small-signal model and compared with other compensations in terms of settling speed. Moreover, to verify the effect of gain peaking on settling speed, two pipeline ADCs employing HMCC and CCNSP are fabricated in a 0.11-μm CMOS process. In measurement, the ADCs with HMCC achieve higher spurious free dynamic range (SFDR) at the sampling frequencies above 20 MHz than the ADCs with CCNSP, which demonstrates that the proposed HMCC achieves faster settling than CCNSP due to gain peaking suppression.

The problem of parameter mismatch in time-interleaved-analog-to-digital converters (TI-ADCs) has become a significant concern to guarantee output linearity. Several solutions have been presented for offset, gain, time skew, and bandwidth mismatches, but they can rely on hardware expensive methods. This article proposes an all-digital calibration algorithm for the TI-ADC bandwidth mismatch, which is capable of detecting the optimal correction coefficients for the derivative-based digital filters. The analyzed convergence logic further relaxes the hardware requirements. Moreover, numerical simulations and experimental results validate the calibration efficiency. A commercial 12-bit 3.6-GS/s two-channel TI-ADC was used to verify the proposed calibration algorithm under real conditions.

In this paper, the analog front end (AFE) for an inductive position sensor in an automotive electromagnetic resonance gear control applications is presented. To improve the position detection accuracy, a coil driver with an automatic two-step impedance calibration is proposed which, despite the load variation, provides the desired driving capability by controlling the main driver size. Also, a time shared analog-to-digital converter (ADC) is proposed to convert eight-phase signals while reducing the current consumption and area to 1/8 of the conventional structure. A relaxation oscillator with temperature compensation is proposed to generate a constant clock frequency in vehicle temperature conditions. This chip is fabricated using a 0.18-$\mu \text{m}$CMOS process and the die area is 2 mm$\times 1.5$mm. The power consumption of the AFE is 23.1 mW from the supply voltage of 3.3 V to drive one transmitter (Tx) coil and eight receiver (Rx) coils. The measured position detection accuracy is greater than 99.8 %. The measurement of the Tx shows a driving capability higher than 35 mA with respect to the load change.

This brief presents a semiblind and foreground calibration method for correcting linear and memoryless errors in pipelined analog-to-digital converters (ADCs). We formulate the calibration problem that finds optimal radices for maximizing signal-to-noise-distortion ratio as a linear fractional programming, a special type of convex optimization problem. The method is further extended to the case when the exact amplitude of a calibration signal is unknown. By utilizing the structure of the calibration signal, it is shown that the optimal radices can be obtained by solving the formulated calibration problem via bisection algorithm. Simulation results indicate that the proposed calibration method can correct linear errors in a hypothetical 14-bit 400 MS/s pipelined ADC using only ≈1600 data samples.