In this paper we address the severe performance gap caused by high processor clock rates and slow DRAM accesses. We show that even with an aggressive, next-generation memory system using four Direct Rambus channels and an integrated one-megabyte level-two cache, a processor still spends over half of its time stalling for L2 misses. Large cache blocks can improve performance, but only when coupled with wide memory channels. DRAM address mappings also affect performance significantly. We evaluate an aggressive prefetch unit integrated with the L2 cache and memory, controllers. By issuing prefetches only when the Rambus channels are idle, prioritizing them to maximize DRAM row buffer hits, and giving them low replacement priority, we achieve a 43% speedup across 10 of the 26 SPEC2000 benchmarks, without degrading performance an the others. With eight Rambus channels, these ten benchmarks improve to within 10% of the performance of a perfect L2 cache.

A previous evaluation of scheduled region prefetching showed that this technique eliminates the bulk of main-memory stall time for applications with spatial locality. The downside to that aggressive prefetching scheme is that, even when it successfully improves performance, it increases enormously the amount of superfluous memory traffic generated by a program. We measure the predictability of spatial locality using density vectors, bit vectors that track the block-level access pattern within a region of memory. We evaluate a number of policies that use density vector information to filter out prefetches that are unlikely to be useful. We show that, across our benchmarks, an average of 70% of useless prefetches can be eliminated with virtually no overall performance loss from reduced coverage. Thanks to the increase in prefetch accuracy, a few benchmarks show performance improvements as high as 35% over the base region prefetching scheme.

In this paper, we address the severe performance gap caused by high processor clock rates and slow DRAM accesses. We show that, even with an aggressive, next-generation memory system using four Direct Rambus channels and an integrated one-megabyte level-two cache, a processor still spends over half its time stalling for L2 misses. Our experimental analysis begins with an effort to tune our baseline memory system aggressively: incorporating optimizations to reduce DRAM row buffer misses, reordering miss accesses to reduce queuing delay, and adjusting the L2 block size to match each channel organization. We show that there is a large gap between the block sizes at which performance is best and at which miss rate is minimized. Using those results, we evaluate a hardware prefetch unit integrated with the L2 cache and memory controllers. By issuing prefetches only when the Rambus channels are idle, prioritizing them to maximize DRAM row buffer hits, and giving them low replacement priority, we achieve a 65 percent speedup across 10 of the 26 SPEC2000 benchmarks, without degrading the performance of the others. With eight Rambus channels, these 10 benchmarks improve to within 10 percent of the performance of a perfect L2 cache.

In this paper, we propose a speech recognition algorithm which utilizes hidden Markov models (HMM) and Viterbi algorithm for segmenting the input speech sequence, such that the variable-dimensional speech signal is converted into a fixed-dimensional speech signal, called TN vector. We then use the fuzzy perceptron to generate hyperplanes which separate patterns of each class from the others. The proposed speech recognition algorithm is easy for speaker adaptation when the idea of "supporting pattern" is used. The supporting patterns are those patterns closest to the hyperplane. When a recognition error occurs, we include all the TN vectors of the input speech sequence with respect to the segmentations of all HMM models as the supporting patterns. The supporting patterns are then used by the fuzzy perceptron to tune the hyperplane that can cause correct recognition, and also tune the hyperplane that resulted in wrong recognition. Since only two hyperplane need to be tuned for a recognition error, the proposed adaptation scheme is time-economic and suitable for on-line adaptation. Although the adaptation scheme cannot ensure to correct the wrong recognition right after adaptation, the hyperplanes are tuned in the direction for correct recognition iteratively and the speed of adaptation can be adjusted by a "belief" parameter set by the user. Several examples are used to show the performance of the proposed speech recognition algorithm and the speaker adaptation scheme.