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Simon Deleonibus

dblp:69/2196 · DBLP profile ↗
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4ranked-venue papers
2as first author
0since 2021 · last 2016
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Applied, interdisciplinary, general and emerging computing · 3 · 2 first-authorSystems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Emerging computing paradigms · 57% Integrated circuit design · 43%

Topics — the 3 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Emerging computing paradigms
nanoelectronics
0.212016
Looking into the future of Nanoelectronics in the Diversification Efficient Era · Sci. China Inf. Sci. 2016
Integrated circuit design › technology scaling
CMOS scaling
0.112011
Ultra-thin films and multigate devices architectures for future CMOS scaling · Sci. China Inf. Sci. 2011
Integrated circuit design › semiconductor devices
multi-gate devices
0.112011
Ultra-thin films and multigate devices architectures for future CMOS scaling · Sci. China Inf. Sci. 2011
YearPublicationVenuePosition
2016 Looking into the future of Nanoelectronics in the Diversification Efficient Era
Simon Deleonibus
Sci. China Inf. Sci.1
2016 Editor's note
Ru Huang 0001, Hiroshi Iwai, Cor Claeys, Simon Deleonibus, Runsheng Wang
Sci. China Inf. Sci.4
2011 3D monolithic integration
abstract
3D monolithic integration, thanks to its high vertical density of interconnections, is the only available option for applications requiring connections at the transistor scale. However to achieve 3D monolithic integration, some issues such as realization of high quality top film, high stability bottom FET, low thermal budget top FET still have to be solved. In this work, a 3D monolithic process flow relying on molecular wafer bonding is proposed and results in all critical steps are given. Significant breakthroughs have been obtained using a full wafer molecular bonding with thin interlayer dielectric and an original salicidation process stabilized up to 650°C enabling to reach high performance for the top and bottom transistor. With such technology, we demonstrate functional top and bottom transistors as well as 3D structures such as invertors and SRAMs.
Perrine Batude, Maud Vinet, Arnaud Pouydebasque, Cyrille Le Royer, Bernard Previtali, Claude Tabone, Jean-Michel Hartmann, Loïc Sanchez, Laurence Baud, Veronique Carron, Alain Toffoli, Fabienne Allain, Vincent Mazzocchi, Dominique Lafond, Simon Deleonibus, Olivier Faynot
ISCAS15
2011 Ultra-thin films and multigate devices architectures for future CMOS scaling
Simon Deleonibus
Sci. China Inf. Sci.1