This paper describes a project dedicated to developing an improved (in terms of usability) version of our previous telecommunication-oriented field programmable gate array (FPGA), and its applications. To achieve this goal, we adopt several challenging design strategies. First, we determine the new FPGA architecture based on a quantitative evaluation carried out to optimize the interaction between the FPGA and CAD algorithms. In addition, we create a new chip design environment that allows semi-automatic test pattern generation and cross-checking between logic and layout design. Furthermore, a dedicated CAD system is developed based on a consideration of the evaluation results and the characteristics of the FPGA. As a result of these design strategies, the FPGA and CAD system are well-balanced, and even though the FPGA has very rich routing resources, the routing process can be finished quickly without sacrificing application-circuit performance. The FPGA is applied to several reconfigurable systems for telecommunications, and is found to offer the required functions and good performance.

In designing FPGAs, it is important to achiev e a good balance bet w een the number of logic blocks, suc h has Look-Up Tables (LUTs), and wiring resources. It is difficult to find an optimal solution. In this paper, w e presen t an FPGA design methodology to efficiently find well-balanced FPGA architectures. The method covers all aspects of FPGA development from the architecture-decision process to physical implementation. It has been used to develop a new FPGA that can implement circuits that are twice as large as those implementable with the previous version but with half the number of logic blocks. This indicates that the methodology is effectiv e in dev eloping well-balanced FPGAs.

We propose an FPGA architecture for next generation B-ISDN telecommunications systems. Such a system requires an FPGA in which an over 10 K gates circuit can be implemented and that has a clock cycle rate of 80 MHz. While the FPGA architecture has been discussed in terms of its circuit structure, we consider the circuit structure of the FPGA with its CAD tools. We evaluate several FPGA logic-element structures with a technology mapping method. From our experiments, the multiplexer based logic-element is found to be suitable for implementing such a high-speed circuit using the BDD-based technology mapping method.

This paper discusses a new approach to efficient system design verification that uses an FPGA based real-time emulator. The architecture of a real-time emulator suitable for high-speed digital transmission system emulation and an experimental system are described. The proposed system consists of an emulation engine using the custom designed multi-chip module FPGA called PROTEUS-MCM, a program control unit, and a physical interface. The system can be used not only for real-time emulation of high-speed transmission systems, but also as initial systems for actual communication networks.

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