Demo Data from EDBT 2026 / reviewers in the wild / expert
Stephen Alan Herrod
dblp:69/2725
· DBLP profile ↗
2ranked-venue papers
0as first author
0since 2021 · last 1995
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Software engineering, systems software and programming languages · 2Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Performance modeling and evaluation · 44% Memory systems · 28% Parallel and multicore computing · 28% | |
| Software engineering, system software, and programming languages
2 papers |
Operating systems · 100% |
Topics — the 6 heaviest of 8, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Memory systems
cache coherence |
0.0 | 2 | 1995 | Memory System Performance of UNIX on CC-NUMA Multiprocessors · SIGMETRICS 1995 The Impact of Architectural Trends on Operating System Performance · SOSP 1995 |
Operating systems
operating system performance |
0.0 | 1 | 1995 | The Impact of Architectural Trends on Operating System Performance · SOSP 1995 |
Parallel and multicore computing › task scheduling › dynamic scheduling
dynamically-scheduled processor |
0.0 | 1 | 1995 | The Impact of Architectural Trends on Operating System Performance · SOSP 1995 |
Performance modeling and evaluation › simulation › computer system simulation
machine simulation |
0.0 | 1 | 1995 | The Impact of Architectural Trends on Operating System Performance · SOSP 1995 |
Performance modeling and evaluation
simulation |
0.0 | 1 | 1995 | The Impact of Architectural Trends on Operating System Performance · SOSP 1995 |
Parallel and multicore computing
multiprocessor system |
0.0 | 1 | 1995 | The Impact of Architectural Trends on Operating System Performance · SOSP 1995 |
Methods — techniques the papers use, named apart from their topics
performance measurement · 0.0SimOS simulation · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1995 | Memory System Performance of UNIX on CC-NUMA Multiprocessors
John Chapin, Stephen Alan Herrod, Mendel Rosenblum, Anoop Gupta |
SIGMETRICS | 2 |
| 1995 | The Impact of Architectural Trends on Operating System PerformanceabstractComputer systems are rapidly changing.Over the next few years, we will see wide-scale deployment of dynamically-scheduled processors that can issue multiple instructions every clock cycle, execute instructions out of order, and overlap computation and cache misses.We also expect clock-rates to increase, caches to grow, and multiprocessors to replace uniprocessors.Using SimOS, a complete machine simulation environment, this paper explores the impact of the above architectural trends on operating system performance.We present results based on the execution of large and realistic workloads (program development, transaction processing, and engineering compute-server) running on the IRIX 5.3 operating system from Silicon Graphics Inc.Looking at uniprocessor trends, we find that disk 1/0 is the first-order bottleneck for workloads such as program development and transaction processing.Its importance continues to grow over time.Ignoring 1/0, we find that the memory system is the key bottleneck, stalling the CPU for over 50% of the execution time.Surprisingly, however, our results show that this stall fraction is unlikely to increase on future machines due to increased cache sizes and new latency hiding techniques in processors.We also find that the benefits of these architectural trends spread broadly across a majority of the important services provided by the operating system.We find the situation to be much worse for multiprocessors.Most operating systems services consume 3f)-i'0~0 more time than their uniprocessor counterparts.A large fraction of the stalls are due to coherence misses caused by communication between processors.Because larger caches do not reduce coherence misses, the performance gap between uniprocessor and multiprocessor performance will increase unless operating system developers focus on kernel restructuring to reduce unnecessary communication.The paper presents a detailed decomposition of execution time (e.g., instruction execution time, memory stall time separately for instructions and data, synchronization time) for important kernel services in the three workloads. Mendel Rosenblum, Edouard Bugnion, Stephen Alan Herrod, Emmett Witchel, Anoop Gupta |
SOSP | 3 |