Presents an architecture for the efficient encoding of Reed-Solomon codes, with or without interleaving. This architecture utilizes a clock whose rate is r times the symbol rate, where r is the redundancy of the code. The finite field operations are performed in a sequential manner, requiring only one finite field multiplier and one finite field adder. All memory elements (except one symbol register) are consolidated into a discrete-time delay line, which can be easily implemented with a random access memory. This approach alleviates the clock skew problem and leads to significant hardware savings over the usual parallel approach, when the redundancy and/or interleaving depth are large. The architecture can be easily reconfigured for changes in the generator polynomial of the code, the amount of redundancy, and the interleaving depth.>

A seven-chip set which performs the functions associated with video and image compression algorithms, and CCITT H.261 in particular, has been designed, fabricated, and is fully functional. The major functions performed by the devices include motion estimation, DCT and IDCT, forward and inverse quantization, Huffman coding and decoding, BCH error correction, and loop filtering. The chips that perform the predictive and transform coding section of the algorithm operate with pixel rates up to 40 MHz. Array-based technologies of 1.5 and 1.0 mu m CMOS were used extensively to achieve a 28 man-month design time. Each die is less than 10 mm on a side.>

The tradeoffs involved in the design of a real-time 40-MHz fast Fourier transform (FFT) chip set are discussed. Tradeoffs involving the algorithmic organization, device partitioning, the data format, and device architecture are examined. The chip set can compute FFTs with up to 2048 points at 40-MHz data rates (or 80-MHz data rates for real data) by using up to 20 chips or at 3-MHz rates when using only three devices. The 1.5- mu CMOS chip set has been designed, fabricated, and tested and is fully functional.>

A set of 1.5- mu m (0.9- mu m effective channel length) CMOS integrated circuits has been designed, fabricated, and tested which perform real-time 20-MHz digital signal processing (DSP). The set includes an 8-bit, 64-tap transversal filter (MFIR); a 1-bit, 1024-tap transversal filter and template matcher (BFIR); a 12-bit, 64-tap rank-value filter (RVF); and an 8-line 512-pixel variable-length video shift register (VSR). The chip set is fully functional and operates at 20 MHz. All components in the family can be used together or in a stand-alone fashion. To enhance the flexibility of the processors, each has a reconfigurable window to allow both one-dimensional and two-dimensional processing. The window size and/or the data and coefficient precision of the two transversal filters can be increased by using multiple processors without the need for external components.>

The authors describe the architecture and design of a high-speed CMOS VLSI filter processor. The internal architecture of the design is pipelined to achieve a sustained 20-MHz data throughput rate. This translates into an effective computational rate of 1.2 billion multiplications (and a similar number of additions) per second. The chip is reconfigurable for one- and two-dimensional filtering, the total device count is 240000 transistors, and the die size is 1.4 cm*1.4 cm. Tap design, data-flow organization, and clock distribution are discussed.>

We have designed, fabricated and tested several special purpose chips which perform a range of image processing tasks. All operate in real-time (10 MHz for a 512 × 512 image) and require no external storage. Dedicated architectures along with pipelining and parallelism are extensively utilized to achieve real-time performance. This is in contrast to many image processing systems that require large arrays of general purpose processing chips [1] or non-real-time systems that use a single high speed data-path. To demonstrate the use of the circuits, they are being put into a system designed to recognize two-dimensional images (figure 1) that are characterized by their closed contours.

In order to reduce the design time of digital filter bank circuits, a design system has been developed. The software consists of the filter compiler which converts high level filter descriptions to hardware descriptions and the layout generator which converts the hardware descriptions to a layout file. To verify the algorithms before fabrication, a test system is employed. The development time of this system was kept to a minimum by designing the hardware to be easily micro coded and assembled. Several circuits have been fabricated and tested that were generated with this system, including a single bandpass filter chip, a 112-pole 16-channel filter bank for a speech recognition system and a 16-channel spectrum analyzer for consumer stereo applications. The speech recognition chip achieved a SNR of 80 dB with an area of 25 mm /sup 2/ in a 4-micron NMOS technology.