Embedded SW design can be compared to the lawless wild west. With no clear methodology and no standard multi core platform modeling environment every company has to improvise its own solution. The problems facing embedded software users are becoming more complex since:

Test generator algorithms may be classified by the level of circuit description they utilize. Algorithms based on a logic-gate level description of the circuit under test (CUT) are the most common. Functional algorithms utilize a functional description of the CUT. Functional test generation techniques may provide better defect coverages than do purely logic-level techniques. Multilevel test generation algorithms attempt to realize the advantages of both approaches by utilizing fault translation. Here, gate-level faults are translated to functional faults and test generation is performed at the functional level. In this paper, we develop and present new techniques for fast efficient fault translation from the logic to the functional level. These techniques are implemented in a multilevel sequential circuit test generation system. The performance of the system is investigated on benchmark circuits.

Recent results indicate that functional test pattern generation (TPG) techniques may provide better defect coverages than do traditional logic-level techniques.Functional TPG algorithms utilize a functional description of a circuit.Multilevel TPG algorithms attempt to realize the advantages of both approaches through fault translation.In such systems, gate-level faults are translated to functional faults and TPG is performed at the functional level.We develop and present new techniques for fast ecient fault translation from the logic to the functional level.These techniques are implemented in a m ulti-level sequential circuit test generation system.Performance results for benchmark circuits are presented. 31

A graph-theoretic formulation for memory repair in the presence of clustered faults is presented. This approach is based on the use of variable-cell-size grids (VCS grids). As VCS grids can be represented by bipartite graphs, the reconfiguration problem for clustered faults can also be formulated as a vertex covering problem. Hence, graph-based reconfiguration algorithms developed by previous authors can be extended to exploit clustered fault distributions. Algorithms for memory repair that do not suffer from the restrictions imposed by previous algorithms for clustered faults are developed. A heuristic repair algorithm that has both improved performance and lower execution time than previous repair algorithms is presented.>