Computing systems working in harsh environment is prone to suffer from radiation-induced soft errors; for example, Single Event Upsets (SEUs) and Single Event Transients (SETs) are the major reliability issue for circuits fabricated with nanoscale technology nodes. In this paper, we proposed a low-cost SET and SEU error tolerant flip-flop (SETU-TOFF). Based on the traditional flip-flop, two high-level sensitive redundant latches are added to latch the input data at different times, and a voter is designed for the correct output. It removes the timing overhead of temporal redundancy from the critical path of the systems. Comparing with the existing designs presented in literatures, SETU-TOFF has comprehensive fault tolerant capability with lower overheads; moreover, it doesn’t increase significant latency of the flip-flops. We use the SETU-TOFF cells to protect a pipeline of an OpenRISC microprocessor. Fault injection simulations show that SETU-TOFF can achieve 100% protection for the pipeline with negligible performance loss; additionally, it can detect and correct errors in real time without extra system control logic and clocks for errors recovery.

As technology scaling down, the sensitivity of SRAM cells to radiation-induced Single Event Upsets (SEUs) increases, and Single Event Multiple Node Upsets (SEMNUs) due to charge sharing has also become one of the major concerns in memory cell designs. In this paper, a high-reliability radiation hardened memory cell (RH-14T) is proposed to mitigate SEMNUs. SPICE simulations and 3D technology computer aided design mixed-mode simulations were performed to verify the high robustness of the RH-14T cell to SEUs. Compared with previous radiation hardened memory cells, the proposed RH-14T cell has similar read access time, smaller write access time, and the read access time and write access time are less sensitive to process variations. The Read Static Noise Margin (RSNM) and Write Margin (WM) of the RH-14T cell are larger than those of the unhardened conventional 6T SRAM cell. The improvement of reliability is often a trade-off with area, power consumption and performance. In order to achieve high reliability, the RH-14T cell employs more transistors, so it has 1.5 times the power consumption overhead of 6T and a larger area penalty.

Field programmable gate array (FPGA) is becoming more valuable for space applications because of its large density, high performance, reduced development cost and flexible programmability. In particular, static random access memory (SRAM) based FPGA is very valuable for remote missions because of the possibility of being reprogrammed by the user as many times as necessary in a very short period. However, SRAM-based FPGA contains a large number of memory cells which are very sensitive to single event upset (SEU). SEU in SRAM-based FPGA may result in a functional error unless the FPGA is reconfigured. In this paper, we propose a fast adjustable scrubbing method based on Xilinx essential bits technology to mitigate the effect of SEU for SRAM-based FPGA. The whole scrubbing flow contains two sub-flows: partial scrubbing and entire scrubbing. This scrubbing method not only increases the speed of repairing an error for user design, but also ensures the reliability of whole FPGA design. We test the proposed scrubbing method through fault injection. Finally, we show the error repair speeds of user designs for different repeat cycles of partial scrubbing and summarize the optimized repeat cycles of partial scrubbing.

Visual tracking is one of the most challenging computer vision problems. In order to achieve high performance visual tracking in various negative scenarios, a novel cascaded Siamese network is proposed and developed based on two different deep learning networks: a matching subnetwork and a classification subnetwork. The matching subnetwork is a fully convolutional Siamese network. According to the similarity score between the exemplar image and the candidate image, it aims to search possible object positions and crop scaled candidate patches. The classification subnet-work is designed to further evaluate the cropped candidate patches and determine the optimal tracking results based on the classification score. The matching subnetwork is trained offline and fixed online, while the classification subnetwork performs stochastic gradient descent online to learn more target-specific information. To improve the tracking performance further, an effective classification subnetwork update method based on both similarity and classification scores is utilized for updating the classification subnetwork. Extensive experimental results demonstrate that our proposed approach achieves state-of-the-art performance in recent benchmarks.

In the last decade, a number of Single Error Correction Double Adjacent Error Correction (SEC-DAEC) codes have been proposed to protect memories against Multiple Cell Upsets (MCUs). These codes are able to correct errors that affect two adjacent bits that is one of the most common MCU patterns. However, soft errors can also affect the encoder and decoder circuitry creating data corruption. An alternative to protect the encoders is to use parity prediction Concurrent Error Detection (CED) to detect errors and avoid writing erroneous words in the memory. This approach has been previously studied for Orthogonal Latin Square (OLS) codes and for matrix codes. In this paper, the implementation of parity prediction Concurrent Error Detection (CED) for SEC-DAEC codes is considered. To that end, first it is shown that CED has a significant cost for the existing SEC-DAEC codes. This is because they are odd weight codes and parity prediction is much simpler for even weight codes. Based on that observation, even weight SEC-DAEC codes are designed and evaluated. The results show that CED can be efficiently implemented in the proposed codes that achieve a significant reduction in encoder circuit complexity compared to previously proposed SEC-DAEC codes.

Radiation-induced single event transients (SETs) are expected to evolve to single event multiple transients (SEMTs) due to the downscaling of transistor feature size, which also increases the difficulty of the vulnerability estimation for large-scale digital integrated circuits. In this paper, a novel layout-based soft error vulnerability estimation approach which is termed LBSEVEA is proposed to evaluate the impact of heavy ions on the vulnerability of combinational circuits. The physical process of interaction between particles and devices, especially nuclear reaction and scattering process are included in the LBSEVEA. In addition, ambipolar diffusion and bipolar amplification effect, which induce additional charge collection of the adjacent transistors and the hitting transistor, are also considered. A new method calculating the collected charge induced by the bipolar amplification effect is presented. By introducing the layout information of the target circuits into the identification of the adjacent cells, SEMTs effect can be considered in the vulnerability estimation. A fast SPICE simulation tool is adopted to conduct the fault injected netlist simulations, which can make a favorable compromise between the consumption of computer resources and simulation precision. Furthermore, induced soft error numbers, distributions of charge collected by the hitting nodes and the adjacent nodes, and SET pulse width distributions are presented. Besides, heatmaps of induced pulse widths for the layout of two benchmark circuits are provided. Finally, the constraints, the flexibility, and the scalability of the LBSEVEA are discussed. The ability to estimate the impact of process variations on the vulnerability is also presented. Compared with simulation and experimental results, the LBSEVEA can fairly estimate the vulnerability of combinational circuits.

Compared with visible object tracking, thermal infrared (TIR) object tracking can track an arbitrary target in total darkness since it cannot be influenced by illumination variations. However, there are many unwanted attributes that constrain the potentials of TIR tracking, such as the absence of visual color patterns and low resolutions. Recently, structured output support vector machine (SOSVM) and discriminative correlation filter (DCF) have been successfully applied to visible object tracking, respectively. Motivated by these, in this paper, we propose a large margin structured convolution operator (LMSCO) to achieve efficient TIR object tracking. To improve the tracking performance, we employ the spatial regularization and implicit interpolation to obtain continuous deep feature maps, including deep appearance features and deep motion features, of the TIR targets. Finally, a collaborative optimization strategy is exploited to significantly update the operators. Our approach not only inherits the advantage of the strong discriminative capability of SOSVM but also achieves accurate and robust tracking with higher-dimensional features and more dense samples. To the best of our knowledge, we are the first to incorporate the advantages of DCF and SOSVM for TIR object tracking. Comprehensive evaluations on two thermal infrared tracking benchmarks, i.e. VOT-TIR2015 and VOT-TIR2016, clearly demonstrate that our LMSCO tracker achieves impressive results and outperforms most state-of-the-art trackers in terms of accuracy and robustness with sufficient frame rate.

Soft errors caused by particle strike in combinational circuits are a major concern in the design of reliable circuits. Particle strike induced single event transient (SET), especially the evolutional single event multiple transients (SEMTs) in nanoscale CMOS technologies, has been the non-negligible reliability issue for hardening design of combinational circuits. This paper presents a low overhead method to protect combinational circuits against particle strike. This method is made up of a combination of two sub-method: (1) a soft error sensitivity estimation method, called Layout-Based Multiple Event Probability Propagation (LBMEPP) and (2) a protection method based on gate sizing, called Intelligent optimization-Based Gate Sizing (IOBGS). Unlike the previous techniques that either overlook the SEMTs event or exploit fault injection. LBMEPP can provide the sensitivity estimation of combinational circuits in the presence of SET and SEMTs. The SEMTs adjacent cells are identified by the cell's layout and Geant4 Monte Carlo simulation. Therefore, the SEMTs event can be considered in the sensitivity estimation. Using the estimation result of LBMEPP, IOBGS adopts multi-objective particle swarm optimization algorithm to dynamically allocate and adjust each logical cells. In IOBGS, SER, circuit area and longest path delay of the circuit are selected as the optimization goals. The experiments conducted on several typical circuits show that the proposed optimization method can evidently decrease the SER with a limited overhead.

The use of error-correction codes (ECCs) with advanced correction capability is a common system-level strategy to harden the memory against multiple bit upsets (MBUs). Therefore, the construction of ECCs with advanced error correction and low redundancy has become an important problem, especially for adjacent ECCs. Existing codes for mitigating MBUs mainly focus on the correction of up to 3-bit burst errors. As the technology scales and cell interval distance decrease, the number of affected bits can easily extend to more than 3 bit. The previous methods are therefore not enough to satisfy the reliability requirement of the applications in harsh environments. In this paper, a technique to extend 3-bit burst error-correction (BEC) codes with quadruple adjacent error correction (QAEC) is presented. First, the design rules are specified and then a searching algorithm is developed to find the codes that comply with those rules. The ${H}$ matrices of the 3-bit BEC with QAEC obtained are presented. They do not require additional parity check bits compared with a 3-bit BEC code. By applying the new algorithm to previous 3-bit BEC codes, the performance of 3-bit BEC is also remarkably improved. The encoding and decoding procedure of the proposed codes is illustrated with an example. Then, the encoders and decoders are implemented using a 65-nm library and the results show that our codes have moderate total area and delay overhead to achieve the correction ability extension.

In this paper, the effect of negative bias temperature instability (NBTI) on MBUs sensitivity of 65 nm bulk technology memories is analyzed and simulated by Geant4. A MTTF reliability model including NBTI stress time is proposed for memories protected by error correction codes (ECCs). Both cases of scrubbing and nonscrubbing are considered. By using the proposed model, the predicted MTTF results align well with the simulation MTTF results in the radiation environment.

The use of error-correcting codes is a common strategy to protect memories from errors. Single-error correction, double-error detection linear block codes have been traditionally utilized. However, there are applications where multiple errors are frequent and more complex codes are needed. Orthogonal Latin square codes are one type of codes with multiple-error-correction capability. They are of interest for memory protection because they can be decoded with low complexity and delay. This paper presents a modification to orthogonal Latin square codes that reduces the number of parity check bits to be stored in memory therefore lowering the memory overhead needed to implement the codes. The proposed codes can also be decoded with low delay and complexity. This paper also presents an evaluation of the encoder and decoder implementations for various word sizes and compares them with the standard orthogonal Latin square implementations. The results show that they are similar in terms of circuit area and introduce only a small penalty in delay.

In this paper, a novel radiation-hardened-by-design (RHBD) 12T memory cell is proposed to tolerate single node upset and multiple-node upset based on upset physical mechanism behind soft errors together with reasonable layout-topology. The verification results obtained confirm that the proposed 12T cell can provide a good radiation robustness. Compared with 13T cell, the increased area, power, read/write access time overheads of the proposed 12T cell are -18.9%, -23.8%, and 171.6%/-50.0%, respectively. Moreover, its hold static noise margin is 986.2 mV which is higher than that of 13T cell. This means that the proposed 12T cell also has higher stability when it provides fault tolerance capability.

Memories that operate in harsh environments, like for example space, suffer a significant number of errors. The error correction codes (ECCs) are routinely used to ensure that those errors do not cause data corruption. However, ECCs introduce overheads both in terms of memory bits and decoding time that limit speed. In particular, this is an issue for applications that require strong error correction capabilities. A number of recent works have proposed advanced ECCs, such as orthogonal Latin squares or difference set codes that can be decoded with relatively low delay. The price paid for the low decoding time is that in most cases, the codes are not optimal in terms of memory overhead and require more parity check bits. On the other hand, codes like the (24,12) Golay code that minimize the number of parity check bits have a more complex decoding. A compromise solution has been recently explored for Bose-Chaudhuri-Hocquenghem codes. The idea is to implement a fast parallel decoder to correct the most common error patterns (single and double adjacent) and use a slower serial decoder for the rest of the patterns. In this brief, it is shown that the same scheme can be efficiently implemented for the (24,12) Golay code. In this case, the properties of the Golay code can be exploited to implement a parallel decoder that corrects single- and double-adjacent errors that is faster and simpler than a single-error correction decoder. The evaluation results using a 65-nm library show significant reductions in area, power, and delay compared with the traditional decoder that can correct single and double-adjacent errors. In addition, the proposed decoder is also able to correct some triple-adjacent errors, thus covering the most common error patterns.

Transient multiple cell upsets (MCUs) are becoming major issues in the reliability of memories exposed to radiation environment. Error correction codes (ECCs) are commonly used to protect memories against MCUs. Among ECCs, matrix codes have obvious advantages due to the simplicity of the encoding and decoding algorithm that enables low overheads. However, an important issue is that when ECCs are used, the encoder and decoder circuits also suffer from errors which affect the reliability of the memory systems. In this paper, low overhead fault secure encoder and decoder designs for matrix codes are proposed to protect encoder and decoder. By using the properties of the parity check matrix of matrix codes, the proposed designs efficiently implement a parity prediction scheme with low overheads. They can detect all errors deriving from a single node in encoder and decoder circuits. A fault secure memory system is established and evaluated, and the obtained results show that the proposed scheme has lower area and power overheads.

Radiation-induced single event upsets (SEUs), or soft errors, have become a dominant factor in the reliability degradation of nanoscale memories. In this paper, based on the SEU physics mechanism, and reasonable layout-topology, a novel soft error hardened memory cell is proposed in 65 nm Complementary Metal Oxide Semiconductor (CMOS) technology. The design comparisons for several hardened memory cells in terms of access time (read access time and write access time), power consumption, and layout area are also executed. The main advantage of the proposed cell is that it can provide 100% fault tolerance, which is very useful for memory applications in severe radiation environments. Furthermore, Monte Carlo simulations are carried out to evaluate the effects of process, voltage, and temperature (PVT) variations. From simulations, we confirmed that the proposed cell has exhibited a sufficient multiple-node upset tolerance capability even under PVT variations.

Transient multiple cell upsets (MCUs) are becoming major issues in the reliability of memories exposed to radiation environment. To prevent MCUs from causing data corruption, more complex error correction codes (ECCs) are widely used to protect memory, but the main problem is that they would require higher delay overhead. Recently, matrix codes (MCs) based on Hamming codes have been proposed for memory protection. The main issue is that they are double error correction codes and the error correction capabilities are not improved in all cases. In this paper, novel decimal matrix code (DMC) based on divide-symbol is proposed to enhance memory reliability with lower delay overhead. The proposed DMC utilizes decimal algorithm to obtain the maximum error detection capability. Moreover, the encoder-reuse technique (ERT) is proposed to minimize the area overhead of extra circuits without disturbing the whole encoding and decoding processes. ERT uses DMC encoder itself to be part of the decoder. The proposed DMC is compared to well-known codes such as the existing Hamming, MCs, and punctured difference set (PDS) codes. The obtained results show that the mean time to failure (MTTF) of the proposed scheme is 452.9%, 154.6%, and 122.6% of Hamming, MC, and PDS, respectively. At the same time, the delay overhead of the proposed scheme is 73.1%, 69.0%, and 26.2% of Hamming, MC, and PDS, respectively. The only drawback to the proposed scheme is that it requires more redundant bits for memory protection.

This letter proposes a novel coordinate rotation digital computer (CORDIC)-based fast radix-2 algorithm for computation of discrete cosine transformation (DCT). The proposed algorithm has some distinguish advantages, such as Cooley-Tukey fast Fourier transformation (FFT)-like regular data flow, uniform post-scaling factor, in-place computation and arithmetic-sequence rotation angles. Compared to existing DCT algorithms, this proposed algorithm has lower computational complexity. Furthermore, the proposed algorithm is highly scalable, modular, regular, and suitable for pipelined VLSI implementation. In addition, this letter also provides an easy way to implement the reconfigurable or unified architecture for DCTs and inverse DCTs.

Nowadays, multiple bit upsets (MBUs) have been widely investigated in memories. Conventional single error correction and double error detection (SEC-DED) codes are capable of correcting one error and detecting all possible double errors. However, they may not provide adequate protection against MBUs. This paper proposes new single-error-correction, double-error-detection double-adjacent-error-correction (SEC-DED-DAEC) codes to mitigate radiation or noise source induced MBUs in memories. The proposed SEC-DED-DAEC codes are obtained from conventional SEC-DED codes according to the mathematics model established in this paper. They can detect and correct all adjacent double bit errors and assure a lower miscorrection probability for non-adjacent double bit errors compared with other SEC-DED-DAEC codes. Furthermore, the redundancy bits of the proposed scheme are the same as those of conventional SEC-DED codes. This means that the increase of correct-capability do not cause additional hardware overhead for the memory system. Finally, the experiment results reveal that the proposed scheme reduces the miscorrection probability of non-adjacent double bit errors by 12% compared to the best known SEC-DED-DAEC codes. Moreover, compared to the well known BCH codes, the proposed scheme reduces 40% hardware redundancy and keeps an acceptable reliability.

Power gating is one of most effective ways to suppress the leakage power in CMOS digital circuits. In this paper, we propose a new method to estimate the maximum instantaneous current (MIC), and derive an analytical model for the MIC of the clusters in distributed sleep transistor network (DSTN) power-gated circuits. Based on this MIC estimation model, we perform ST sizing in DSTN power-gated circuits. Experimental results show that we have achieved higher precision and less runtime.

A radiation harden technique based on gate sizing and multi-objective genetic algorithm (MOGA) is developed to optimize the soft error tolerance of standard cell circuits. Soft error rate (SER), chip area and longest path delay are selected as the optimization goals and fast fitness evaluation algorithms for the three goals are developed and embedded into the MOGA. All the three goals are optimized simultaneously by optimally sizing the gates in the circuit, which is a complex NP-Complete problem and resolved by MOGA through exploring the global design space of the circuit. Syntax analysis technique is also employed to make the proposed framework can optimize not only pure combinational logic circuit but also the combinational parts of sequential logic circuit. Optimizing experiments carried out on ISCAS'85 and ISCAS'89 standard benchmark circuits show that the proposed optimization algorithm can decrease the SER 74.25% with very limited delay overhead (0.28%). Furthermore, the algorithm can also reduce the area for most of the circuit under test by average 5.23%. The proposed technique is proved to be better than other works in delay and area overhead and suitable to direct the design of soft error tolerance integrated circuits in high reliability realms.

Fault injection in circuit level has proved to be cumbersome and time-consuming when employed to characterize the soft error sensitivity of digital circuits, hence new generation of CAD tool is required to automate the faults insertion and the validation of soft error mitigation mechanisms of the circuits. This paper outlines the characteristics of a new fault-injection platform HSECT-SPI (HIT Soft Error Characterization Toolkit-Spice Based) and its evaluation in some benchmark circuits implemented with distinct processes and soft error hardening techniques. It also details some techniques devised and implemented within the platform to automate and speed-up the circuit level fault-injection experiments. Experimental results are provided, showing that the platform is efficient, accurate and can direct the design of soft error immune circuits with at least three orders of magnitudes speed gain.

This paper proposes a configurable TAM-Bus, a P1500 compliant Test Access Mechanism (TAM), and the TAM-Bus controller (TAM-controller) that is interfaced with JTAG at chip level of chip. All IP (Intellectual Property) cores' test can be controlled through the TAP under the control of the TAM-controller. The test architecture we presented has been implemented in an industry SoC. The test coverage remains 99.40%. The overhead increases only 0.17% due to TAM. The experiment results demonstrate that the test architecture can offer the solution for testing SoC.

Capable and efficiency simulators are in demand for designing complex analog and mixed-signal circuits and systems. With the standardization of VHDL-AMS, the demand is being realized. VHDL-AMS is an Analog and Mixed-Signal Extensions to VHDL. This paper introduces a mixed-signal simulator for it. The simulator was developed on the original VHDL digital simulation environment. An analog kernel has been integrated into the environment for the simulation of the continuous behavior of a model. The paper presents the algorithms adopted in the analog kernel and the synchronization of the digital and analog executions. The performance of the simulator is examined by mixed-signal examples.