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Rajani M. Kant

dblp:69/4851 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1978
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Parallel and multicore computing · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Parallel and multicore computing › parallel algorithms
matrix computation
0.011978
Decentralized Parallel Algorithms for Matrix Computation · ISCA 1978
Parallel and multicore computing › parallel architecture
mesh-connected computer
0.011978
Decentralized Parallel Algorithms for Matrix Computation · ISCA 1978
Parallel and multicore computing › parallel algorithms › parallel matrix algorithms
parallel matrix inversion
0.011978
Decentralized Parallel Algorithms for Matrix Computation · ISCA 1978

Methods — techniques the papers use, named apart from their topics

sylvester's theorem · 0.0message routing · 0.0
YearPublicationVenuePosition
1978 Decentralized Parallel Algorithms for Matrix Computation
abstract
It is shown that a mesh-connected n×n multiprocessor system can compute the inverse of a n×n matrix in linear time to n. The algorithm is based on a theorem known to Sylvester in 1851. It computes the cofactor matrix in n steps, each of which involves 4 unit distance message routing and 4 arithmetic operations for every processor. A coding and memory requirement for each processor is the same and is independent of n.It is also shown that the same algorithm solves systems of n linear equations in linear time of n with n × (n+l) processors.
Rajani M. Kant, Takayuki Kimura
ISCA1