For wireline transmitters (TX), the traditional architecture would introduce a large amount of parasitic capacitance and reduce the bandwidth of the output stage. Strict timing constraints for retiming units in FFE arrays would also limit speed and consume extra power. In this paper, we propose an analog-MUX-based architecture with a small capacitance load of output drivers and inherent FFE without strict timing constraints. Only one full-speed node makes it easy to use inductors to extend bandwidth. The expanded output bandwidth ensures the TX to reach a comparable operating speed with advanced technology even in traditional planar technologies. A CML clock path with switched inductors is proposed to cover the full frequency band. Implemented in a 65nm CMOS process, the TX with 112Gb/s PAM4 data rate and 3.14pJ/bit efficiency is achieved. The data rate can be further improved with more advanced process nodes.

This paper analyzes the relationship between the total output noise power and loop filter coefficients variation of continuous-time delta-sigma modulators. Based on the analysis, a new calibration technique utilizing the total output noise power to improve the loop filter inaccuracy caused by PVT variation is proposed. This proposed calibration method is implemented in the digital domain and requires only capacitor arrays in analog loop, minimizing the hardware cost and the excess loop delay. The calibration technique is verified by a third-order delta-sigma modulator post-layout simulation results. The peak signal-to-noise-and-distortion ratio (SNDR) increased by 4.5dB after calibration.

This paper presents a multi-band front-end module (FEM) with a built-in transmit/receive (T/R) switch in 28 nm standard CMOS technology for 5G NR communication. A T/R switch topology is proposed to separate the design processes of the power amplifier (PA) and the low noise amplifier (LNA), which reduces the insertion loss in Tx mode caused by the T/R switch. To enable cover the all 5G NR bands at 28 GHz and 39 GHz, a four-coupled inductor-based reconfigurable inductor is used to shift the operational band in the interstage matching network of the low noise amplifier (LNA) and power amplifier (PA). Identical signal paths are used for both the LNA and PA. The FEM consists of a two-stage pseudo-differential PA with a cascade output stage to obtain high output power, a single-end LNA with two-stage cascade to achieve high power gain, and a compact and relatively low insertion loss T/R switch. The measured OP1dB and PAEOP1dB in Tx mode are 17.42 dBm and 16.36%, respectively. The measured NFmin in Rx mode is 5.65 dB. A 64-QAM 600 MSym/s single-carrier was measured in Tx mode.

This article presents two Ka-band low-noise amplifiers (LNA) for millimeter-wave (mm-wave) phased-arrays. The folded three-coil transformer and electrical-magnetic (EM) dual-feedforward techniques are proposed to improve the LNA’s noise performance and reduce the chip area. Design procedures targeting compact chip area, low noise, and high gain are provided. The first two-stage single-ended LNA, consisting of a common-gate (CG) input stage and a common-source (CS) output stage, achieves 1.9 dB minimum noise figure (NF), 16.7 dB peak gain, 4.3 GHz 3 dB bandwidth (BW) from 25.6 to 29.9 GHz, and$-$12 dBm input 1-dB gain-compression-point (IP1dB) with 13.2 mW power consumption. The second LNA employs the current-reuse topology based on the first LNA, which reduces the power consumption to 3.6 mW at the cost of 0.6 dB NF degradation. The proposed LNAs have been fabricated in 65 nm CMOS process. The two LNAs have the same 200$\mu $m$\times$300$\mu $m core chip area. To the best of our knowledge, the first LNA shows the lowest NF and smallest core area at 28 GHz compared with the published CMOS works in a similar frequency range.

An IEEE 802.15.4/4z standard compliant all-digital UWB transmitter with a fast-settling master-slave voltage regulator is presented in this paper. The proposed digital transmitter (DTX) with the master-slave regulator reduces the power supply crosstalk from the all-digital transmitter operation, which contributes to maintaining decent TX power spectral density (PSD). In addition, the deterioration of DTX PSD is avoided by synchronization of the data stream in the LO domain and the alignment of AM/PM paths in the DTX. Furthermore, wide-band transformer-based impedance matching is introduced in the DTX to achieve high output power with high efficiency while performing the differential-to-single-ended conversion. The presented UWB DTX has been designed in a 28nm CMOS and covers from 6.5 to 8 GHz (Ch5 to Ch9). The DTX achieves 13-dBm TX peak power. The transmitted pulse complies with FCC and ETSI regulations achieving 71% spectrum efficiency and -32-dBr sidelobe suppression.

This article presents a compact 24–30-GHz four-element phased-array transceiver (TRx) front-end (FE) for 5-G communications. A compact T/R switch co-designed with power amplifier’s (PA) output matching network and low-noise amplifier’s (LNA) input matching network is proposed. Leveraging the transformers in the two matching networks, only one extra transistor switch is needed, which greatly reduces the chip area consumption and therefore the insertion loss. A bidirectional phase shifter composed of a two-stage polyphase filter (PPF) and two bidirectional variable-gain amplifiers (BVGA) is shared by both TX and RX. The 24–30-GHz four-element TRx FE is implemented in 65-nm CMOS process. The TX path including the power splitter and T/R switch achieves a measured 11.5-/16.5-dBm OP1dB/PSAT with 12.2%/22.9% PAE$_{\mathrm {1 dB}}$/PAEMAX with 35.1-dB gain. The RX path including power combiner, T/R switch, and off-mode PA achieves a minimum 5.1-dB noise figure (NF) with 25.8-dB gain. The TX and RX paths achieve 5.625° phase resolution with$ < 2^{\circ }$/0.4-dB rms phase/gain error as well as 30.6-dB gain control range with 0.5-dB gain step and$ < 1.5^{\circ }$/0.26-dB rms phase/gain error over 24–30 GHz. Under the 64-QAM fifth-generation (5G) NR FR2 orthogonal frequency division multiplexing (OFDM) measurements, the TX path achieves an average output power of 0 dBm per element (2.1% PAE) with 8.66% EVM, and the RX path achieves an average 4.96% EVM, making the proposed TRx FE suitable for 5G NR FR2 applications. The chip size excluding pads is$4.1\times4.0$mm.

This paper presented a 76–81 GHz FMCW MIMO Radar transceiver with mixed-mode PLL. Utilizing series-fed patch antenna array, a prototype system is developed based on the proposed transceiver. On-chip Measurements show that reconfigurable sawtooth chirps could be generated with a bandwidth up to 4 GHz and a period as short as 30${\mu s}$. Real-time experiments demonstrate that the prototype MIMO radar has the ability of target detection and achieves an angular resolution of 9°

This work presents a linearized Ka-band heterodyne receiver for millimeter-wave phased-array systems with high linearity requirement. A folded class-AB inductive peaking mixer and a two-stage magnetic self-cancellation-based load-pull interstage matching Intermediate-frequency (IF) amplifier are proposed to improve the linearity of input and output 1-dB compression point, respectively. The proposed receiver is implemented in 65 nm CMOS technology and its core area is 0.7 mm2. The measured input 1-dB compression point (IP1dB) is −10.9dBm and the output 1-dB compression point (OP1dB) is 7.1 dBm, with noise Figure (NF) of 10.1 dB at center frequency. To the best knowledge of the authors, the proposed RX achieves the highest IP1dBand OP1dBamong all the listed publications in silicon technology. The power consumption of the receiver including LO path is 119mW.

An energy-efficient millimeter-wave transceiver with direct-modulation digital transmitter (TX), I/Q phase-coupled frequency synthesizer and Substrate-Integrated Waveguide (SIW) E-shaped patch antenna is presented in this paper. The proposed transceiver achieves the 10-Gbps data rate while consuming 340.4 mW. The measured Over-the-Air (OTA) EVM is -13.8 dB. The energy efficiency is 34 pJ/bit, which is a significant improvement compared with the state-of-the-art mm-wave transceivers.

In this paper, a fully-synthesizable digital-to-time (DTC)-based fractional-Nmultiplying delay-locked loop(MDLL) is presented. Noise and linearity of synthesizable DTCs are analyzed, and a two-stage synthesizable DTC is proposed in which a path-selection DTC is used as the coarse stage and a variable-slope DTC is used as the fine stage. To calibrate the DTC nonlinearity, a highly robust zero-order interpolation based nonlinearity calibration is proposed. Besides, the static phase offsets (SPO) between bang-bang phase detector (BBPD) and multiplexer (MUX) are calibrated by a proposed hybrid analog/digital phase offset calibration, while the dynamic phase offsets (DPO) are removed by a proposed complementary switching scheme. The co-design of the analog circuits and digital calibrations enable excellent jitter and spur performance. The MDLL achieves 0.70 and 0.48ps root-mean-square (RMS) jitter in fractional-N and integer-N modes, respectively. The fractional spur is less than -59.0dBc, and the reference spur is -64.5dBc. The power consumptions are 1.85mW and 1.22mW, corresponding to figures of merit (FOM) of -240.4dB and -245.5dB.

This article presents a small-area Bluetooth Low-Energy (BLE) transceiver (TRX) for short-range Internet-of-Things (IoT) applications in 65-nm CMOS. An integrated Radio-Frequency Input-Output (RFIO) circuitry embedded with transmitter/receiver (TX/RX) switch function and on-chip impedance matching is proposed. A hybrid-loop TRX structure based on a wide-bandwidth fractional-N digital phase-locked loop (DPLL) is implemented to achieve the maximum power reduction. A -94dBm receiver sensitivity is achieved with 2.3mW receiver power consumption, while a RF receiving bypass route integration enhances the input power tolerance. The BLE transceiver delivers -6dBm output power while consuming 2.6mW and delivers 0dBm output power while achieving 18.5% maximum TX efficiency. Thanks to the RFIO with harmonic suppression, -56dBc of 2nd-order harmonic distortion (HD2) and -48dBc of 3rd-order harmonic distortion (HD3) suppression are achieved with 0.85mm2on-chip area. This transceiver satisfied the BLE radio specification without the need for external filters and with low-power consumption, which enables minimum size and long life-time modules.

A 35-GHz transmitter (TX) and receiver (RX) front-ends in CMOS technology for Ka-band frequency-modulated continuous wave (FMCW) phased-array radar transceivers is presented in this paper. In order to mitigate undesired electromagnetic coupling through LC resonators in TX/RX and avoid severe metal density issue in highly scaled CMOS technology, Ka-band RF circuit design strategy using transmission line is studied. To improve the TX output power level, a power amplifier (PA) with 4-way power splitter/combiner and transmission line for impedance transforming is introduced. The proposed TX and RX front-ends is designed and fabricated in a 65nm CMOS technology. The measured TX output power is 19 dBm. The RX achieves a conversion gain of 29.6 dB. The TX occupies 1.42 mm2and consumes 588 mW. The RX occupies 0.59 mm2and consumes 72mW.

A 4.25-4.65 GHz LC-VCO with tailing filter technique integrating an 8-shaped inductor with an orthogonal-coupled tail-filtering inductor is presented in this paper. The mutual inductance between the 8-shaped inductor and the tail-filtering inductor is negligible due to the symmetrical and reversal magnetic field by the two loops of the 8-shaped inductor, which avoids the additional chip area occupation of the bulky tail-filtering inductor. The VCO is implemented in TSMC 180 nm CMOS process, obtaining a tuning range (TR) of 0.4 GHz, which consumes 7.7 mA current from a 1 V power supply. By adopting the 8-shaped inductor and noise filtering technique from the orthogonal-coupled inductor, the post-layout simulated phase noise achieves -126.7 dBc/Hz at 1 MHz offset away from the 4.4 GHz carrier and the resulting figure-of-merit (FoM) is -191 dB.

A 35-GHz transmitter (TX) and receiver (RX) front end in CMOS technology for Ka-band frequency-modulated continuous wave (FMCW) phased-array radar transceivers are presented in this article. While typical FMCW phased-array radar transceivers use RF-path phase-shifting scheme for both TX and RX front ends, the Ka-band TX and RX front ends presented in this article are designed for TX-analog and RX-digital beamforming phased-array radar system. The link budget for the Ka-band phased-array radar transceiver is investigated. In order to improve the TX output power level, a power amplifier (PA) with a four-way power splitter/combiner is introduced. The detailed analyses and design considerations of the PA are investigated. The proposed TX and RX front ends are implemented and fabricated in a 1P9M 65-nm CMOS technology. The measured TX output power is 19 dBm. To the best of authors' knowledge, it is the highest output power FMCW module at the Ka-band using CMOS technology reported so far. The RX achieves a conversion gain of 29.6 dB. The TX occupies 1.42 mm2and consumes 588 mW. The RX occupies 0.59 mm2and consumes 72 mW.

This paper presents an HDL-synthesized injection-locked phase-locked loop using LC-based DCO for on-chip clock generation. The superior noise performance of the LC-DCO enables the proposed synthesizable PLL to achieve top performance among the existing designs. Fabricated in a 65nm CMOS process, this prototype demonstrates a 0.142ps integrated jitter at 3.0GHz and consumes 4.6mW while only occupying an area of 0.12mm2. It achieves a figure of merit (FoM) of -250.3dB, which is the best for the synthesized PLL up-to-date.

This paper presents an automatic place-and-routed two-stage fractional-N injection-locked PLL (IL-PLL) using soft injection technique for on-chip clock generation. Fabricated in a 65nm CMOS process, this prototype demonstrates a 3.6-ps integrated jitter at 1.5222 GHz and consumes 3mW leading to an FoM of -224.6 dB while only occupying an area of 0.048 mm2. It realizes the first fully synthesized fractional-N injection-locked PLL up-to-date.

This paper proposes a tail-current modulated VCO with adaptive-bias scheme. The proposed adaptive-bias scheme ensures robust startup conditions for the tail-feedback VCO. A tail-feedback VCO using the proposed scheme is implemented in a 0.18-μm CMOS process. The measured phase noise is -119.3dBc/Hz at 1MHz offset with a power dissipation of 6.8mW at 4.6GHz.

This paper presents a low power and low noise sub-harmonically injection-locked PLL using a 20GHz sub-sampling PLL (SS-PLL) and a quadrature injection locked oscillator (QILO). Lower in-band phase noise and out-of-band phase noise have been achieved through the sub-sampling phase detection and sub-harmonic injection techniques, respectively. Implemented in a 65nm CMOS, this work can support all 60GHz channels and achieves a phase noise of -115dBc/Hz at 10MHz offset while consuming 20.2mW and 14mW from the 20GHz SS-PLL and the QILO, respectively.

This paper presents a small area, low power, fully synthesizable PLL with a current output DAC and an interpolative-phase coupled oscillator using edge injection technique for on-chip clock generation. A prototype PLL is fabricated in a 65nm digital CMOS process, achieves a 1.7-ps integrated jitter at 0.9 GHz and consumes 0.78 mW leading to an FOM of -236.5 dB while only occupying an area of 0.0066 mm2. It achieves the best performance-area trade-off.

This paper presents a compact, low power, and low jitter dual-loop injection-locked PLL with synthesizable all-digital background calibration system for clock generation. Implemented in a 65nm CMOS process, this work demonstrates a 0.7-ps RMS jitter at 1.2 GHz while having 0.97-mW power consumption resulting in an FOM of -243dB. It also consumes an area of only 0.022mm2resulting in the best performance-area trade-off system presented up-to-date.

A swing-enhanced current-reuse class-C VCO which can theoretically achieve same phase noise figure-of-merit (FoM) as other class-C VCOs at the lowest power consumption is presented. A swing enhancement in class-C operation and an oscillation robustness are achieved through dynamic bias control circuits for both NMOS and PMOS transistors. The proposed VCO has been fabricated in 180nm CMOS process while oscillating at 4.6 GHz. The measured phase noise is -119 dBc/Hz at 1 MHz offset while consuming 1.6 mA from 1.5 V supply. An FoM of -189 dBc/Hz is achieved.

This paper presents an area-efficient frequency synthesizer with a quadrature phase output using a fractional-N injection-locking technique for software-defined radios. A background calibration scheme is proposed to compensate for the PVT variations. Implemented in a 65nm CMOS process, this work demonstrates 10 MHz to 6.6 GHz continuous quadrature frequency coverage, while only occupies a small area of 0.38 mm2and consumes 16-26 mW depending on output frequency, from a 1.2 V power supply. The normalized phase noise achieves -135.3 dBc/Hz at 3 MHz offset, and -95.1 dBc/Hz in-band phase noise at 10 kHz offset, from a 1.7 GHz carrier frequency.

A 58.1-to-65.0 GHz frequency synthesizer using sub-harmonic injection-locking technique is presented. The synthesizer can generate all 60GHz channels defined by IEEE 802.15.3c, wirelessHD, IEEE 802.11ad, WiGig, and ECMA-387. A frequency calibration scheme is proposed to monitor frequency shift resulting from environmental variations. Implemented in a 65nm CMOS process, the synthesizer achieves a typical phase noise of -117 dBc/Hz @10MHz offset from a carrier frequency of 61.56 GHz.

This paper presents a feedback class-C VCO with PVT-robustness and enhanced oscillation swing. The proposed VCO starts oscillation as a differential LC-VCO for robust startup, and automatically adapts to an amplitude-enhanced class-C VCO in steady-state for lower phase noise. The proposed VCO is implemented in a 0.18μm CMOS process. The measured phase noise at room temperature is -125 dBc/Hz @ 1MHz offset with a power dissipation of 3.4-mW, from a carrier frequency of 4.84-GHz. The figure-of-merit is -193 dBc/Hz.

This paper proposes a 0.5-V LC-VCO with a frequency extension circuit to replace ring oscillators for ultra-low-voltage sub-1ps-jitter clock generation. Significant performances, in terms of 0.6-ps jitter, 50MHz-to-6.4GHz frequency tuning range with 2 bands and sub-1mW PDC, indicates the successful replacement of ring VCO for the future 0.5-V LSIs and power aware LSIs.